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/freebsd/sys/contrib/device-tree/Bindings/interconnect/
H A Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Bus and Interconnect
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The Samsung Exynos SoC has many buses for data transfer between DRAM and
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
16 Generally, each bus of Exynos SoC includes a source clock and a power line,
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/freebsd/sys/contrib/device-tree/Bindings/devfreq/
H A Dexynos-bus.txt1 * Generic Exynos Bus frequency device
3 The Samsung Exynos SoC has many buses for data transfer between DRAM
4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
5 for buses. Generally, each bus of Exynos SoC includes a source clock
7 of the bus in runtime. To monitor the usage of each bus in runtime,
9 is able to measure the current load of sub-blocks.
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
12 The each AXI bus has the owned source clock but, has not the only owned
13 power line. The power line might be shared among one more sub-blocks.
14 So, we can divide into two type of device as the role of each sub-block.
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/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos5433-bus.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC Memory interface and AMBA bus device tree source
11 compatible = "samsung,exynos-bus";
13 clock-names = "bus";
14 operating-points-v2 = <&bus_g2d_400_opp_table>;
19 compatible = "samsung,exynos-bus";
21 clock-names = "bus";
22 operating-points-v2 = <&bus_g2d_266_opp_table>;
27 compatible = "samsung,exynos-bus";
29 clock-names = "bus";
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/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
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H A Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos
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H A Dexynos4x12.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos
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H A Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
46 bus_dmc: bus-dmc {
47 compatible = "samsung,exynos-bus";
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H A Dexynos4.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
19 #include <dt-bindings/clock/exynos4.h>
20 #include <dt-bindings/clock/exynos-audss-clk.h>
21 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/interrupt-controller/irq.h>
25 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <1>;
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/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Dsamsung,sysmmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
10 - Marek Szyprowski <m.szyprowski@samsung.com>
13 Samsung's Exynos architecture contains System MMUs that enables scattered
14 physical memory chunks visible as a contiguous region to DMA-capable peripheral
15 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
20 another capabilities like L2 TLB or block-fetch buffers to minimize translation
24 peripheral device might have multiple System MMUs (usually one for each bus
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/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dsamsung,exynos-adc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/samsung,exynos-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos Analo
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/freebsd/sys/contrib/device-tree/Bindings/display/samsung/
H A Dsamsung,exynos-mixer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos
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H A Dsamsung,exynos-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC HDMI
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-hdmi
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/freebsd/sys/contrib/device-tree/Bindings/soc/samsung/
H A Dexynos-usi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung's Exynos USI (Universal Serial Interface)
10 - Sam Protsenko <semen.protsenko@linaro.org>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The USI IP-core provides configurable support for serial protocols, enabling
18 simultaneously in select combinations - High-Speed I2C0, High-Speed
19 I2C1, SPI, UART, High-Speed I2C0 and I2C1 or both High-Speed
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/freebsd/sys/contrib/device-tree/Bindings/devfreq/event/
H A Dsamsung,exynos-nocp.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-nocp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos NoC (Network on Chip) Probe
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The Samsung Exynos542x SoC has a NoC (Network on Chip) Probe for NoC bus.
19 traffic debug or statistic collectors. Exynos542x bus has multiple NoC probes
25 const: samsung,exynos5420-nocp
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/freebsd/sys/contrib/device-tree/Bindings/display/exynos/
H A Dexynos_hdmi.txt1 Device-Tree bindings for drm hdmi driver
4 - compatible: value should be one among the following:
5 1) "samsung,exynos4210-hdmi"
6 2) "samsung,exynos4212-hdmi"
7 3) "samsung,exynos5420-hdmi"
8 4) "samsung,exynos5433-hdmi"
9 - reg: physical base address of the hdmi and length of memory mapped
11 - interrupts: interrupt number to the cpu.
12 - hpd-gpios: following information about the hotplug gpio pin.
16 - ddc: phandle to the hdmi ddc node
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsamsung,exynos-audss-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos-audss-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Audio SubSystem clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
17 include/dt-bindings/clock/exynos-audss-clk.h header.
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H A Dsamsung,exynosautov9-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos Auto v9 SoC clock controller
10 - Chanho Park <chanho61.park@samsung.com>
11 - Chanwoo Choi <cw00.choi@samsung.com>
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - Tomasz Figa <tomasz.figa@gmail.com>
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/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-exynos5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-exynos5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
17 e.g. for Exynos850 and Exynos Auto V9 SoCs), it might be also necessary to
19 Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml for details.
24 - enum:
25 - samsung,exynos5250-hsi2c # Exynos5250 and Exynos5420
26 - samsung,exynos5260-hsi2c # Exynos5260
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H A Dsamsung,s3c2410-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/samsung,s3c2410-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC I2C Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - enum:
16 - samsung,s3c2410-i2c
17 - samsung,s3c2440-i2c
18 # For s3c2440-like I2C used inside HDMIPHY block found on several SoCs:
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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dexynos-dw-mshc.txt1 * Samsung Exynos specific extensions to the Synopsys Designware Mobile
7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
25 - "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific
28 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
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H A Dsamsung,exynos-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Samsung Exynos SoC specific extensions to the Synopsys Designware Mobile
12 - Jaehoon Chung <jh80.chung@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - enum:
19 - axis,artpec8-dw-mshc
20 - samsung,exynos4210-dw-mshc
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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dexynos-usb.txt1 Samsung Exynos SoC USB controller
3 The USB devices interface with USB controllers on Exynos SOCs.
8 - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupts: interrupt number to the cpu.
13 - clocks: from common clock binding: handle to usb clock.
14 - clock-names: from common clock binding: Shall be "usbhost".
15 - phys: from the *Generic PHY* bindings; array specifying phy(s) used
17 - phy-names: from the *Generic PHY* bindings; array of the names for
22 - samsung,vbus-gpio: if present, specifies the GPIO that
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H A Dsamsung,exynos-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/samsung,exynos-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC USB 2.0 EHCI/OHCI Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - samsung,exynos4210-ehci
16 - samsung,exynos4210-ohci
21 clock-names:
23 - const: usbhost
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dexynos-srom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC SROM Controller driver
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 extra properties, describing the bus behind it, should be specified.
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dsamsung-fimc.txt1 Samsung S5P/Exynos SoC Camera Subsystem (FIMC)
2 ----------------------------------------------
4 The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices
6 the S5P SoCs series known as CAMIF), MIPI CSIS, FIMC-LITE and FIMC-IS (ISP).
8 The sub-subdevices are defined as child nodes of the common 'camera' node which
10 any single sub-device, like common camera port pins or the CAMCLK clock outputs
14 --------------------
18 - compatible: must be "samsung,fimc", "simple-bus"
19 - clocks: list of clock specifiers, corresponding to entries in
20 the clock-names property;
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