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/freebsd/sys/arm64/coresight/
H A Dcoresight_tmc.c168 bus_write_4(sc->res, TMC_DBALO, event->etr.low); in tmc_configure_etr()
169 bus_write_4(sc->res, TMC_DBAHI, event->etr.high); in tmc_configure_etr()
170 bus_write_4(sc->res, TMC_RSZ, event->etr.bufsize / 4); in tmc_configure_etr()
172 bus_write_4(sc->res, TMC_RRP, event->etr.low); in tmc_configure_etr()
173 bus_write_4(sc->res, TMC_RWP, event->etr.low); in tmc_configure_etr()
203 dprintf(dev, "ETR configuration found\n"); in tmc_init()
241 if (event->etr.flags & ETR_FLAG_ALLOCATE) { in tmc_enable()
242 event->etr.flags &= ~ETR_FLAG_ALLOCATE; in tmc_enable()
270 if (event->etr.flags & ETR_FLAG_RELEASE) { in tmc_disable()
271 event->etr.flags &= ~ETR_FLAG_RELEASE; in tmc_disable()
[all …]
H A Dcoresight.h140 struct etr_state etr; member
H A Dcoresight_etm4x.c57 * CPU0 -> ETM0 -> funnel1 -> funnel0 -> ETF -> replicator -> ETR -> DRAM
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Darm,coresight-tmc.yaml24 FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
25 mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.
68 Size of contiguous buffer space for TMC ETR (embedded trace router). The
75 Indicates that the TMC-ETR can safely use the SG mode on this system.
100 description: AXI or ATB Master output connection. Used for ETR
115 etr@20070000 {
H A Dcoresight.txt23 Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
24 configuration. The configuration mode (ETB, ETF, ETR) is
123 * arm,buffer-size: size of contiguous buffer space for TMC ETR
127 * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
192 etr@20070000 {
H A Darm,embedded-trace-extension.yaml19 components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
H A Dete.yaml19 components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dmaxim,max8973.yaml74 maxim,enable-etr:
78 maxim,enable-high-etr-sensitivity:
82 sensitivity. If this property is available then etr will be enable
84 Enhanced transient response (ETR) will affect the configuration of CKADV.
137 maxim,enable-etr;
H A Dmax8973-regulator.txt28 -maxim,enable-etr: boolean, enable Enhanced Transient Response.
29 -maxim,enable-high-etr-sensitivity: boolean, Enhanced transient response
31 property is available then etr will be enable default.
33 Enhanced transient response (ETR) will affect the configuration of CKADV.
/freebsd/sys/arm64/qualcomm/
H A Dqcom_gcc.c49 #define ETR_USB_CBCR_CLK_ENABLE (1 << 0) /* ETR USB clk branch ctrl */
84 /* Enable ETR USB clock branch */ in qcom_qdss_enable()
/freebsd/sys/contrib/device-tree/include/dt-bindings/memory/
H A Dtegra186-mc.h191 /* ETR reads */
193 /* ETR writes */
H A Dtegra194-mc.h211 /* ETR read clients */
213 /* ETR write clients */
H A Dtegra234-mc.h363 /* ETR read clients */
365 /* ETR write clients */
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Djuno-scmi.dtsi14 etr@20070000 {
/freebsd/sys/dev/qat/qat_hw/qat_c62x/
H A Dadf_c62x_hw_data.h72 * BIT(3) enables error detection and reporting on the ETR Parity Error.
/freebsd/sys/dev/qat_c2xxx/
H A Dqatvar.h802 /* ETR */
803 struct qat_bank *sc_etr_banks; /* array of etr banks */
804 struct qat_ap_bank *sc_etr_ap_banks; /* array of etr auto push banks */
H A Dqat_c2xxxreg.h154 /* ETR */
H A Dqat_c2xxx.c105 * ETR rings. Work around that for now by simply in qat_c2xxx_get_ae_mask()
/freebsd/sys/dev/qat/qat_hw/qat_200xx/
H A Dadf_200xx_hw_data.h70 * BIT(3) enables error detection and reporting on the ETR Parity Error.
/freebsd/sys/dev/qat/qat_hw/qat_c3xxx/
H A Dadf_c3xxx_hw_data.h68 * BIT(3) enables error detection and reporting on the ETR Parity Error.
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi3660-coresight.dtsi424 etr@ec033000 {
H A Dhi6220-coresight.dtsi99 etr@f6404000 {
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8998-mtp.dts111 &etr {
H A Dmsm8998-mtp.dtsi81 &etr {
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_per.c429 GATE(ETR, "etr", "clk_m", X(3)),

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