1 /* SPDX-License-Identifier: BSD-2-Clause AND BSD-3-Clause */
2 /* $NetBSD: qat_c2xxx.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $ */
3
4 /*
5 * Copyright (c) 2019 Internet Initiative Japan, Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 /*
31 * Copyright(c) 2007-2013 Intel Corporation. All rights reserved.
32 *
33 * Redistribution and use in source and binary forms, with or without
34 * modification, are permitted provided that the following conditions
35 * are met:
36 *
37 * * Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * * Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in
41 * the documentation and/or other materials provided with the
42 * distribution.
43 * * Neither the name of Intel Corporation nor the names of its
44 * contributors may be used to endorse or promote products derived
45 * from this software without specific prior written permission.
46 *
47 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
48 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
49 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
50 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
51 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
53 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
57 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
58 */
59
60 #include <sys/cdefs.h>
61 #if 0
62 __KERNEL_RCSID(0, "$NetBSD: qat_c2xxx.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $");
63 #endif
64
65 #include <sys/param.h>
66 #include <sys/bus.h>
67 #include <sys/systm.h>
68
69 #include <machine/bus.h>
70
71 #include <dev/pci/pcireg.h>
72 #include <dev/pci/pcivar.h>
73
74 #include "qatreg.h"
75 #include "qat_hw15reg.h"
76 #include "qat_c2xxxreg.h"
77 #include "qatvar.h"
78 #include "qat_hw15var.h"
79
80 static uint32_t
qat_c2xxx_get_accel_mask(struct qat_softc * sc)81 qat_c2xxx_get_accel_mask(struct qat_softc *sc)
82 {
83 uint32_t fusectl;
84
85 fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
86
87 return ((~fusectl) & ACCEL_MASK_C2XXX);
88 }
89
90 static uint32_t
qat_c2xxx_get_ae_mask(struct qat_softc * sc)91 qat_c2xxx_get_ae_mask(struct qat_softc *sc)
92 {
93 uint32_t fusectl;
94
95 fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
96 if (fusectl & (
97 FUSECTL_C2XXX_PKE_DISABLE |
98 FUSECTL_C2XXX_ATH_DISABLE |
99 FUSECTL_C2XXX_CPH_DISABLE)) {
100 return 0;
101 } else {
102 if ((~fusectl & AE_MASK_C2XXX) == 0x3) {
103 /*
104 * With both AEs enabled we get spurious completions on
105 * ETR rings. Work around that for now by simply
106 * disabling the second AE.
107 */
108 device_printf(sc->sc_dev, "disabling second AE\n");
109 fusectl |= 0x2;
110 }
111 return ((~fusectl) & AE_MASK_C2XXX);
112 }
113 }
114
115 static enum qat_sku
qat_c2xxx_get_sku(struct qat_softc * sc)116 qat_c2xxx_get_sku(struct qat_softc *sc)
117 {
118 uint32_t fusectl;
119
120 fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
121
122 switch (sc->sc_ae_num) {
123 case 1:
124 if (fusectl & FUSECTL_C2XXX_LOW_SKU)
125 return QAT_SKU_3;
126 else if (fusectl & FUSECTL_C2XXX_MID_SKU)
127 return QAT_SKU_2;
128 break;
129 case MAX_AE_C2XXX:
130 return QAT_SKU_1;
131 }
132
133 return QAT_SKU_UNKNOWN;
134 }
135
136 static uint32_t
qat_c2xxx_get_accel_cap(struct qat_softc * sc)137 qat_c2xxx_get_accel_cap(struct qat_softc *sc)
138 {
139 return QAT_ACCEL_CAP_CRYPTO_SYMMETRIC |
140 QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC |
141 QAT_ACCEL_CAP_CIPHER |
142 QAT_ACCEL_CAP_AUTHENTICATION;
143 }
144
145 static const char *
qat_c2xxx_get_fw_uof_name(struct qat_softc * sc)146 qat_c2xxx_get_fw_uof_name(struct qat_softc *sc)
147 {
148 if (sc->sc_rev < QAT_REVID_C2XXX_B0)
149 return AE_FW_UOF_NAME_C2XXX_A0;
150
151 /* QAT_REVID_C2XXX_B0 and QAT_REVID_C2XXX_C0 */
152 return AE_FW_UOF_NAME_C2XXX_B0;
153 }
154
155 static void
qat_c2xxx_enable_intr(struct qat_softc * sc)156 qat_c2xxx_enable_intr(struct qat_softc *sc)
157 {
158
159 qat_misc_write_4(sc, EP_SMIA_C2XXX, EP_SMIA_MASK_C2XXX);
160 }
161
162 static void
qat_c2xxx_init_etr_intr(struct qat_softc * sc,int bank)163 qat_c2xxx_init_etr_intr(struct qat_softc *sc, int bank)
164 {
165 /*
166 * For now, all rings within the bank are setup such that the generation
167 * of flag interrupts will be triggered when ring leaves the empty
168 * state. Note that in order for the ring interrupt to generate an IRQ
169 * the interrupt must also be enabled for the ring.
170 */
171 qat_etr_bank_write_4(sc, bank, ETR_INT_SRCSEL,
172 ETR_INT_SRCSEL_MASK_0_C2XXX);
173 qat_etr_bank_write_4(sc, bank, ETR_INT_SRCSEL_2,
174 ETR_INT_SRCSEL_MASK_X_C2XXX);
175 }
176
177 const struct qat_hw qat_hw_c2xxx = {
178 .qhw_sram_bar_id = BAR_SRAM_ID_C2XXX,
179 .qhw_misc_bar_id = BAR_PMISC_ID_C2XXX,
180 .qhw_etr_bar_id = BAR_ETR_ID_C2XXX,
181 .qhw_cap_global_offset = CAP_GLOBAL_OFFSET_C2XXX,
182 .qhw_ae_offset = AE_OFFSET_C2XXX,
183 .qhw_ae_local_offset = AE_LOCAL_OFFSET_C2XXX,
184 .qhw_etr_bundle_size = ETR_BUNDLE_SIZE_C2XXX,
185 .qhw_num_banks = ETR_MAX_BANKS_C2XXX,
186 .qhw_num_ap_banks = ETR_MAX_AP_BANKS_C2XXX,
187 .qhw_num_rings_per_bank = ETR_MAX_RINGS_PER_BANK,
188 .qhw_num_accel = MAX_ACCEL_C2XXX,
189 .qhw_num_engines = MAX_AE_C2XXX,
190 .qhw_tx_rx_gap = ETR_TX_RX_GAP_C2XXX,
191 .qhw_tx_rings_mask = ETR_TX_RINGS_MASK_C2XXX,
192 .qhw_msix_ae_vec_gap = MSIX_AE_VEC_GAP_C2XXX,
193 .qhw_fw_auth = false,
194 .qhw_fw_req_size = FW_REQ_DEFAULT_SZ_HW15,
195 .qhw_fw_resp_size = FW_REQ_DEFAULT_SZ_HW15,
196 .qhw_ring_asym_tx = 2,
197 .qhw_ring_asym_rx = 3,
198 .qhw_ring_sym_tx = 4,
199 .qhw_ring_sym_rx = 5,
200 .qhw_mof_fwname = AE_FW_MOF_NAME_C2XXX,
201 .qhw_mmp_fwname = AE_FW_MMP_NAME_C2XXX,
202 .qhw_prod_type = AE_FW_PROD_TYPE_C2XXX,
203 .qhw_get_accel_mask = qat_c2xxx_get_accel_mask,
204 .qhw_get_ae_mask = qat_c2xxx_get_ae_mask,
205 .qhw_get_sku = qat_c2xxx_get_sku,
206 .qhw_get_accel_cap = qat_c2xxx_get_accel_cap,
207 .qhw_get_fw_uof_name = qat_c2xxx_get_fw_uof_name,
208 .qhw_enable_intr = qat_c2xxx_enable_intr,
209 .qhw_init_etr_intr = qat_c2xxx_init_etr_intr,
210 .qhw_init_admin_comms = qat_adm_ring_init,
211 .qhw_send_admin_init = qat_adm_ring_send_init,
212 .qhw_crypto_setup_desc = qat_hw15_crypto_setup_desc,
213 .qhw_crypto_setup_req_params = qat_hw15_crypto_setup_req_params,
214 .qhw_crypto_opaque_offset =
215 offsetof(struct fw_la_resp, comn_resp.opaque_data),
216 };
217