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/freebsd/sys/contrib/device-tree/Bindings/arm/mediatek/
H A Dmediatek,ethsys.txt1 Mediatek ethsys controller
4 The Mediatek ethsys controller provides various clocks to the system.
9 - "mediatek,mt2701-ethsys", "syscon"
10 - "mediatek,mt7622-ethsys", "syscon"
11 - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
12 - "mediatek,mt7629-ethsys", "syscon"
13 - "mediatek,mt7981-ethsys", "syscon"
14 - "mediatek,mt7986-ethsys", "syscon"
18 The ethsys controller uses the common clk binding from
24 ethsys: clock-controller@1b000000 {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmediatek,net.yaml52 mediatek,ethsys:
413 - mediatek,ethsys
435 <&ethsys CLK_ETH_ESW_EN>,
436 <&ethsys CLK_ETH_GP0_EN>,
437 <&ethsys CLK_ETH_GP1_EN>,
438 <&ethsys CLK_ETH_GP2_EN>,
450 mediatek,ethsys = <&ethsys>;
515 clocks = <&ethsys CLK_ETH_FE_EN>,
516 <&ethsys CLK_ETH_GP2_E
[all...]
H A Dmediatek-net.txt29 - resets: Should contain phandles to the ethsys reset signals
33 - mediatek,ethsys: phandle to the syscon node that handles the port setup
60 <&ethsys CLK_ETHSYS_ESW>,
61 <&ethsys CLK_ETHSYS_GP2>,
62 <&ethsys CLK_ETHSYS_GP1>;
68 resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
70 mediatek,ethsys = <&ethsys>;
/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt7629.dtsi430 ethsys: syscon@1b000000 { label
431 compatible = "mediatek,mt7629-ethsys", "syscon";
445 <&ethsys CLK_ETH_ESW_EN>,
446 <&ethsys CLK_ETH_GP0_EN>,
447 <&ethsys CLK_ETH_GP1_EN>,
448 <&ethsys CLK_ETH_GP2_EN>,
449 <&ethsys CLK_ETH_FE_EN>,
471 mediatek,ethsys = <&ethsys>;
H A Dmt2701.dtsi720 ethsys: syscon@1b000000 { label
721 compatible = "mediatek,mt2701-ethsys", "syscon";
734 <&ethsys CLK_ETHSYS_ESW>,
735 <&ethsys CLK_ETHSYS_GP1>,
736 <&ethsys CLK_ETHSYS_GP2>,
739 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
740 <&ethsys MT2701_ETHSYS_GMAC_RST>,
741 <&ethsys MT2701_ETHSYS_PPE_RST>;
744 mediatek,ethsys = <&ethsys>;
H A Dmt7623.dtsi940 ethsys: syscon@1b000000 { label
941 compatible = "mediatek,mt7623-ethsys",
942 "mediatek,mt2701-ethsys",
953 clocks = <&ethsys CLK_ETHSYS_HSDMA>;
968 <&ethsys CLK_ETHSYS_ESW>,
969 <&ethsys CLK_ETHSYS_GP1>,
970 <&ethsys CLK_ETHSYS_GP2>,
973 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
974 <&ethsys MT2701_ETHSYS_GMAC_RST>,
975 <&ethsys MT2701_ETHSYS_PPE_RST>;
[all …]
H A Dmt7623a.dtsi54 resets = <&ethsys MT2701_ETHSYS_MCM_RST>;
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7986a.dtsi500 ethsys: syscon@15000000 {
503 compatible = "mediatek,mt7986-ethsys",
557 clocks = <&ethsys CLK_ETH_FE_EN>,
558 <&ethsys CLK_ETH_GP2_EN>,
559 <&ethsys CLK_ETH_GP1_EN>,
560 <&ethsys CLK_ETH_WOCPU1_EN>,
561 <&ethsys CLK_ETH_WOCPU0_EN>,
582 mediatek,ethsys = <&ethsys>;
496 ethsys: syscon@15000000 { global() label
H A Dmt7622.dtsi929 ethsys: syscon@1b000000 { label
930 compatible = "mediatek,mt7622-ethsys",
941 clocks = <&ethsys CLK_ETH_HSDMA_EN>;
977 <&ethsys CLK_ETH_ESW_EN>,
978 <&ethsys CLK_ETH_GP0_EN>,
979 <&ethsys CLK_ETH_GP1_EN>,
980 <&ethsys CLK_ETH_GP2_EN>,
992 mediatek,ethsys = <&ethsys>;
/freebsd/sys/contrib/device-tree/Bindings/crypto/
H A Dmediatek-crypto.txt22 clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
/freebsd/sys/contrib/device-tree/include/dt-bindings/reset/
H A Dmt7986-resets.h46 /* ETHSYS Subsystem resets */
H A Dmt2701-resets.h75 /* ETHSYS resets */
H A Dmt7622-reset.h76 /* ETHSYS Subsystem resets */
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dmtk-hsdma.txt27 clocks = <&ethsys CLK_ETHSYS_HSDMA>;
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dmt7986-clk.h161 /* ETHSYS */
H A Dmt7629-clk.h188 /* ETHSYS */
H A Dmediatek,mt7981-clk.h209 /* ETHSYS */
H A Dmt7622-clk.h264 /* ETHSYS */
H A Dmt2701-clk.h415 /* ETHSYS */
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dmediatek,mt7530.yaml151 ethsys.
372 resets = <&ethsys MT2701_ETHSYS_MCM_RST>;
H A Dmt7530.txt29 line index for the ethsys.
/freebsd/sys/contrib/device-tree/src/mips/ralink/
H A Dmt7621.dtsi315 mediatek,ethsys = <&sysc>;