xref: /freebsd/sys/contrib/device-tree/Bindings/net/mediatek,net.yaml (revision aa1a8ff2d6dbc51ef058f46f3db5a8bb77967145) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/mediatek,net.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Frame Engine Ethernet controller
8
9maintainers:
10  - Lorenzo Bianconi <lorenzo@kernel.org>
11  - Felix Fietkau <nbd@nbd.name>
12
13description:
14  The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
15  have dual GMAC ports.
16
17properties:
18  compatible:
19    enum:
20      - mediatek,mt2701-eth
21      - mediatek,mt7623-eth
22      - mediatek,mt7621-eth
23      - mediatek,mt7622-eth
24      - mediatek,mt7629-eth
25      - mediatek,mt7981-eth
26      - mediatek,mt7986-eth
27      - mediatek,mt7988-eth
28      - ralink,rt5350-eth
29
30  reg:
31    maxItems: 1
32
33  clocks: true
34  clock-names: true
35
36  interrupts:
37    minItems: 1
38    maxItems: 4
39
40  power-domains:
41    maxItems: 1
42
43  resets:
44    maxItems: 3
45
46  reset-names:
47    items:
48      - const: fe
49      - const: gmac
50      - const: ppe
51
52  mediatek,ethsys:
53    $ref: /schemas/types.yaml#/definitions/phandle
54    description:
55      Phandle to the syscon node that handles the port setup.
56
57  cci-control-port: true
58
59  mediatek,hifsys:
60    $ref: /schemas/types.yaml#/definitions/phandle
61    description:
62      Phandle to the mediatek hifsys controller used to provide various clocks
63      and reset to the system.
64
65  mediatek,infracfg:
66    $ref: /schemas/types.yaml#/definitions/phandle
67    description:
68      Phandle to the syscon node that handles the path from GMAC to
69      PHY variants.
70
71  mediatek,sgmiisys:
72    $ref: /schemas/types.yaml#/definitions/phandle-array
73    minItems: 1
74    maxItems: 2
75    items:
76      maxItems: 1
77    description:
78      A list of phandle to the syscon node that handles the SGMII setup which is required for
79      those SoCs equipped with SGMII.
80
81  mediatek,wed:
82    $ref: /schemas/types.yaml#/definitions/phandle-array
83    minItems: 2
84    maxItems: 2
85    items:
86      maxItems: 1
87    description:
88      List of phandles to wireless ethernet dispatch nodes.
89
90  mediatek,wed-pcie:
91    $ref: /schemas/types.yaml#/definitions/phandle
92    description:
93      Phandle to the mediatek wed-pcie controller.
94
95  dma-coherent: true
96
97  mdio-bus:
98    $ref: mdio.yaml#
99    unevaluatedProperties: false
100
101  "#address-cells":
102    const: 1
103
104  "#size-cells":
105    const: 0
106
107allOf:
108  - $ref: ethernet-controller.yaml#
109  - if:
110      properties:
111        compatible:
112          contains:
113            enum:
114              - mediatek,mt2701-eth
115              - mediatek,mt7623-eth
116    then:
117      properties:
118        interrupts:
119          maxItems: 3
120
121        clocks:
122          minItems: 4
123          maxItems: 4
124
125        clock-names:
126          items:
127            - const: ethif
128            - const: esw
129            - const: gp1
130            - const: gp2
131
132        mediatek,infracfg: false
133
134        mediatek,pctl:
135          $ref: /schemas/types.yaml#/definitions/phandle
136          description:
137            Phandle to the syscon node that handles the ports slew rate and
138            driver current.
139
140        mediatek,wed: false
141
142        mediatek,wed-pcie: false
143
144  - if:
145      properties:
146        compatible:
147          contains:
148            enum:
149              - mediatek,mt7621-eth
150    then:
151      properties:
152        interrupts:
153          maxItems: 1
154
155        clocks:
156          minItems: 2
157          maxItems: 2
158
159        clock-names:
160          items:
161            - const: ethif
162            - const: fe
163
164        mediatek,infracfg: false
165
166        mediatek,wed: false
167
168        mediatek,wed-pcie: false
169
170  - if:
171      properties:
172        compatible:
173          contains:
174            const: mediatek,mt7622-eth
175    then:
176      properties:
177        interrupts:
178          maxItems: 3
179
180        clocks:
181          minItems: 11
182          maxItems: 11
183
184        clock-names:
185          items:
186            - const: ethif
187            - const: esw
188            - const: gp0
189            - const: gp1
190            - const: gp2
191            - const: sgmii_tx250m
192            - const: sgmii_rx250m
193            - const: sgmii_cdr_ref
194            - const: sgmii_cdr_fb
195            - const: sgmii_ck
196            - const: eth2pll
197
198        mediatek,infracfg: false
199
200        mediatek,sgmiisys:
201          minItems: 1
202          maxItems: 1
203
204        mediatek,pcie-mirror:
205          $ref: /schemas/types.yaml#/definitions/phandle
206          description:
207            Phandle to the mediatek pcie-mirror controller.
208
209        mediatek,wed-pcie: false
210
211  - if:
212      properties:
213        compatible:
214          contains:
215            const: mediatek,mt7629-eth
216    then:
217      properties:
218        interrupts:
219          maxItems: 3
220
221        clocks:
222          minItems: 17
223          maxItems: 17
224
225        clock-names:
226          items:
227            - const: ethif
228            - const: sgmiitop
229            - const: esw
230            - const: gp0
231            - const: gp1
232            - const: gp2
233            - const: fe
234            - const: sgmii_tx250m
235            - const: sgmii_rx250m
236            - const: sgmii_cdr_ref
237            - const: sgmii_cdr_fb
238            - const: sgmii2_tx250m
239            - const: sgmii2_rx250m
240            - const: sgmii2_cdr_ref
241            - const: sgmii2_cdr_fb
242            - const: sgmii_ck
243            - const: eth2pll
244
245        mediatek,sgmiisys:
246          minItems: 2
247          maxItems: 2
248
249        mediatek,wed: false
250
251        mediatek,wed-pcie: false
252
253  - if:
254      properties:
255        compatible:
256          contains:
257            const: mediatek,mt7981-eth
258    then:
259      properties:
260        interrupts:
261          minItems: 4
262
263        clocks:
264          minItems: 15
265          maxItems: 15
266
267        clock-names:
268          items:
269            - const: fe
270            - const: gp2
271            - const: gp1
272            - const: wocpu0
273            - const: sgmii_ck
274            - const: sgmii_tx250m
275            - const: sgmii_rx250m
276            - const: sgmii_cdr_ref
277            - const: sgmii_cdr_fb
278            - const: sgmii2_tx250m
279            - const: sgmii2_rx250m
280            - const: sgmii2_cdr_ref
281            - const: sgmii2_cdr_fb
282            - const: netsys0
283            - const: netsys1
284
285        mediatek,infracfg: false
286
287        mediatek,sgmiisys:
288          minItems: 2
289          maxItems: 2
290
291  - if:
292      properties:
293        compatible:
294          contains:
295            const: mediatek,mt7986-eth
296    then:
297      properties:
298        interrupts:
299          minItems: 4
300
301        clocks:
302          minItems: 15
303          maxItems: 15
304
305        clock-names:
306          items:
307            - const: fe
308            - const: gp2
309            - const: gp1
310            - const: wocpu1
311            - const: wocpu0
312            - const: sgmii_tx250m
313            - const: sgmii_rx250m
314            - const: sgmii_cdr_ref
315            - const: sgmii_cdr_fb
316            - const: sgmii2_tx250m
317            - const: sgmii2_rx250m
318            - const: sgmii2_cdr_ref
319            - const: sgmii2_cdr_fb
320            - const: netsys0
321            - const: netsys1
322
323        mediatek,infracfg: false
324
325        mediatek,sgmiisys:
326          minItems: 2
327          maxItems: 2
328
329  - if:
330      properties:
331        compatible:
332          contains:
333            const: mediatek,mt7988-eth
334    then:
335      properties:
336        interrupts:
337          minItems: 4
338
339        clocks:
340          minItems: 34
341          maxItems: 34
342
343        clock-names:
344          items:
345            - const: crypto
346            - const: fe
347            - const: gp2
348            - const: gp1
349            - const: gp3
350            - const: ethwarp_wocpu2
351            - const: ethwarp_wocpu1
352            - const: ethwarp_wocpu0
353            - const: esw
354            - const: netsys0
355            - const: netsys1
356            - const: sgmii_tx250m
357            - const: sgmii_rx250m
358            - const: sgmii2_tx250m
359            - const: sgmii2_rx250m
360            - const: top_usxgmii0_sel
361            - const: top_usxgmii1_sel
362            - const: top_sgm0_sel
363            - const: top_sgm1_sel
364            - const: top_xfi_phy0_xtal_sel
365            - const: top_xfi_phy1_xtal_sel
366            - const: top_eth_gmii_sel
367            - const: top_eth_refck_50m_sel
368            - const: top_eth_sys_200m_sel
369            - const: top_eth_sys_sel
370            - const: top_eth_xgmii_sel
371            - const: top_eth_mii_sel
372            - const: top_netsys_sel
373            - const: top_netsys_500m_sel
374            - const: top_netsys_pao_2x_sel
375            - const: top_netsys_sync_250m_sel
376            - const: top_netsys_ppefb_250m_sel
377            - const: top_netsys_warp_sel
378            - const: wocpu1
379            - const: wocpu0
380            - const: xgp1
381            - const: xgp2
382            - const: xgp3
383
384        mediatek,sgmiisys:
385          minItems: 2
386          maxItems: 2
387
388patternProperties:
389  "^mac@[0-1]$":
390    type: object
391    unevaluatedProperties: false
392    allOf:
393      - $ref: ethernet-controller.yaml#
394    description:
395      Ethernet MAC node
396    properties:
397      compatible:
398        const: mediatek,eth-mac
399
400      reg:
401        maxItems: 1
402
403    required:
404      - reg
405      - compatible
406
407required:
408  - compatible
409  - reg
410  - interrupts
411  - clocks
412  - clock-names
413  - mediatek,ethsys
414
415unevaluatedProperties: false
416
417examples:
418  - |
419    #include <dt-bindings/interrupt-controller/arm-gic.h>
420    #include <dt-bindings/interrupt-controller/irq.h>
421    #include <dt-bindings/clock/mt7622-clk.h>
422    #include <dt-bindings/power/mt7622-power.h>
423
424    soc {
425      #address-cells = <2>;
426      #size-cells = <2>;
427
428      ethernet: ethernet@1b100000 {
429        compatible = "mediatek,mt7622-eth";
430        reg = <0 0x1b100000 0 0x20000>;
431        interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
432                     <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
433                     <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
434        clocks = <&topckgen CLK_TOP_ETH_SEL>,
435                 <&ethsys CLK_ETH_ESW_EN>,
436                 <&ethsys CLK_ETH_GP0_EN>,
437                 <&ethsys CLK_ETH_GP1_EN>,
438                 <&ethsys CLK_ETH_GP2_EN>,
439                 <&sgmiisys CLK_SGMII_TX250M_EN>,
440                 <&sgmiisys CLK_SGMII_RX250M_EN>,
441                 <&sgmiisys CLK_SGMII_CDR_REF>,
442                 <&sgmiisys CLK_SGMII_CDR_FB>,
443                 <&topckgen CLK_TOP_SGMIIPLL>,
444                 <&apmixedsys CLK_APMIXED_ETH2PLL>;
445        clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
446                      "sgmii_tx250m", "sgmii_rx250m",
447                      "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
448                      "eth2pll";
449        power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
450        mediatek,ethsys = <&ethsys>;
451        mediatek,sgmiisys = <&sgmiisys>;
452        cci-control-port = <&cci_control2>;
453        mediatek,pcie-mirror = <&pcie_mirror>;
454        mediatek,hifsys = <&hifsys>;
455        dma-coherent;
456
457        #address-cells = <1>;
458        #size-cells = <0>;
459
460        mdio0: mdio-bus {
461          #address-cells = <1>;
462          #size-cells = <0>;
463
464          phy0: ethernet-phy@0 {
465            reg = <0>;
466          };
467
468          phy1: ethernet-phy@1 {
469            reg = <1>;
470          };
471        };
472
473        gmac0: mac@0 {
474          compatible = "mediatek,eth-mac";
475          phy-mode = "rgmii";
476          phy-handle = <&phy0>;
477          reg = <0>;
478        };
479
480        gmac1: mac@1 {
481          compatible = "mediatek,eth-mac";
482          phy-mode = "rgmii";
483          phy-handle = <&phy1>;
484          reg = <1>;
485        };
486      };
487    };
488
489  - |
490    #include <dt-bindings/interrupt-controller/arm-gic.h>
491    #include <dt-bindings/interrupt-controller/irq.h>
492    #include <dt-bindings/clock/mt7622-clk.h>
493
494    soc {
495      #address-cells = <2>;
496      #size-cells = <2>;
497
498      eth: ethernet@15100000 {
499        #define CLK_ETH_FE_EN               0
500        #define CLK_ETH_WOCPU1_EN           3
501        #define CLK_ETH_WOCPU0_EN           4
502        #define CLK_TOP_NETSYS_SEL          43
503        #define CLK_TOP_NETSYS_500M_SEL     44
504        #define CLK_TOP_NETSYS_2X_SEL       46
505        #define CLK_TOP_SGM_325M_SEL        47
506        #define CLK_APMIXED_NET2PLL         1
507        #define CLK_APMIXED_SGMPLL          3
508
509        compatible = "mediatek,mt7986-eth";
510        reg = <0 0x15100000 0 0x80000>;
511        interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
512                     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
513                     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
514                     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
515        clocks = <&ethsys CLK_ETH_FE_EN>,
516                 <&ethsys CLK_ETH_GP2_EN>,
517                 <&ethsys CLK_ETH_GP1_EN>,
518                 <&ethsys CLK_ETH_WOCPU1_EN>,
519                 <&ethsys CLK_ETH_WOCPU0_EN>,
520                 <&sgmiisys0 CLK_SGMII_TX250M_EN>,
521                 <&sgmiisys0 CLK_SGMII_RX250M_EN>,
522                 <&sgmiisys0 CLK_SGMII_CDR_REF>,
523                 <&sgmiisys0 CLK_SGMII_CDR_FB>,
524                 <&sgmiisys1 CLK_SGMII_TX250M_EN>,
525                 <&sgmiisys1 CLK_SGMII_RX250M_EN>,
526                 <&sgmiisys1 CLK_SGMII_CDR_REF>,
527                 <&sgmiisys1 CLK_SGMII_CDR_FB>,
528                 <&topckgen CLK_TOP_NETSYS_SEL>,
529                 <&topckgen CLK_TOP_NETSYS_SEL>;
530        clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
531                      "sgmii_tx250m", "sgmii_rx250m",
532                      "sgmii_cdr_ref", "sgmii_cdr_fb",
533                      "sgmii2_tx250m", "sgmii2_rx250m",
534                      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
535                      "netsys0", "netsys1";
536        mediatek,ethsys = <&ethsys>;
537        mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
538        assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
539                          <&topckgen CLK_TOP_SGM_325M_SEL>;
540        assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
541                                 <&apmixedsys CLK_APMIXED_SGMPLL>;
542
543        #address-cells = <1>;
544        #size-cells = <0>;
545
546        mdio: mdio-bus {
547          #address-cells = <1>;
548          #size-cells = <0>;
549
550          phy5: ethernet-phy@0 {
551            compatible = "ethernet-phy-id67c9.de0a";
552            phy-mode = "2500base-x";
553            reset-gpios = <&pio 6 1>;
554            reset-deassert-us = <20000>;
555            reg = <5>;
556          };
557
558          phy6: ethernet-phy@1 {
559            compatible = "ethernet-phy-id67c9.de0a";
560            phy-mode = "2500base-x";
561            reg = <6>;
562          };
563        };
564
565        mac0: mac@0 {
566          compatible = "mediatek,eth-mac";
567          phy-mode = "2500base-x";
568          phy-handle = <&phy5>;
569          reg = <0>;
570        };
571
572        mac1: mac@1 {
573          compatible = "mediatek,eth-mac";
574          phy-mode = "2500base-x";
575          phy-handle = <&phy6>;
576          reg = <1>;
577        };
578      };
579    };
580