Home
last modified time | relevance | path

Searched full:eiointc (Results 1 – 10 of 10) sorted by relevance

/linux/arch/loongarch/kvm/intc/
H A Deiointc.c165 struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc; in kvm_eiointc_read() local
167 if (!eiointc) { in kvm_eiointc_read()
168 kvm_err("%s: eiointc irqchip not valid!\n", __func__); in kvm_eiointc_read()
173 kvm_err("%s: eiointc not aligned addr %llx len %d\n", __func__, addr, len); in kvm_eiointc_read()
180 spin_lock_irqsave(&eiointc->lock, flags); in kvm_eiointc_read()
181 loongarch_eiointc_read(vcpu, eiointc, addr, &data); in kvm_eiointc_read()
182 spin_unlock_irqrestore(&eiointc->lock, flags); in kvm_eiointc_read()
297 struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc; in kvm_eiointc_write() local
299 if (!eiointc) { in kvm_eiointc_write()
300 kvm_err("%s: eiointc irqchip not valid!\n", __func__); in kvm_eiointc_write()
[all …]
H A Dpch_pic.c11 /* update the isr according to irq level and route irq to eiointc */
17 * set isr and route irq to eiointc and in pch_pic_update_irq()
24 eiointc_set_irq(s->kvm->arch.eiointc, irq, level); in pch_pic_update_irq()
30 eiointc_set_irq(s->kvm->arch.eiointc, irq, level); in pch_pic_update_irq()
72 eiointc_set_irq(kvm->arch.eiointc, irq, level); in pch_msi_set_irq()
105 /* only route to int0: eiointc */ in loongarch_pch_pic_read()
/linux/arch/loongarch/boot/dts/
H A Dloongson-2k0500.dtsi90 interrupt-parent = <&eiointc>;
100 interrupt-parent = <&eiointc>;
110 interrupt-parent = <&eiointc>;
120 interrupt-parent = <&eiointc>;
165 eiointc: interrupt-controller@1fe11600 { label
166 compatible = "loongson,ls2k0500-eiointc";
366 interrupt-parent = <&eiointc>;
374 interrupt-parent = <&eiointc>;
382 interrupt-parent = <&eiointc>;
399 interrupt-parent = <&eiointc>;
[all …]
H A Dloongson-2k2000.dtsi96 interrupt-parent = <&eiointc>;
140 eiointc: interrupt-controller@1fe01600 { label
141 compatible = "loongson,ls2k2000-eiointc";
157 interrupt-parent = <&eiointc>;
168 interrupt-parent = <&eiointc>;
/linux/drivers/irqchip/
H A Dirq-loongson-eiointc.c8 #define pr_fmt(fmt) "eiointc: " fmt
214 /* Enable cpu interrupt pin from eiointc */ in eiointc_router_init()
320 * eiointc interrupt controller routes to different cpu interrupt pins in eiointc_irq_dispatch()
363 .name = "EIOINTC",
543 * Only the first eiointc device on VM supports routing to in eiointc_init()
544 * different CPU interrupt pins. The later eiointc devices use in eiointc_init()
545 * generic method if there are multiple eiointc devices in future in eiointc_init()
573 "irqchip/loongarch/eiointc:starting", in eiointc_init()
660 if (of_device_is_compatible(of_node, "loongson,ls2k0500-eiointc")) in eiointc_of_init()
679 IRQCHIP_DECLARE(loongson_ls2k0500_eiointc, "loongson,ls2k0500-eiointc", eiointc_of_init);
[all …]
/linux/Documentation/translations/zh_TW/arch/loongarch/
H A Dirq-chip-model.rst14 Legacy I/O Interrupt Controller）、EIOINTC（Extended I/O Interrupt Controller）、
18 CPUINTC是一種CPU內部的每個核本地的中斷控制器，LIOINTC/EIOINTC/HTVECINTC是CPU內部的
72 | EIOINTC | | LIOINTC | <-- | UARTs |
105 EIOINTC::
154 - EIOINTC：即《龍芯3A5000處理器使用手冊》第11.2節所描述的“擴展I/O中斷”；
/linux/arch/loongarch/kernel/
H A Dacpi.c141 struct acpi_madt_eio_pic *eiointc = NULL; in acpi_parse_eio_master() local
143 eiointc = (struct acpi_madt_eio_pic *)header; in acpi_parse_eio_master()
144 if (BAD_MADT_ENTRY(eiointc, end)) in acpi_parse_eio_master()
147 core = eiointc->node * CORES_PER_EIO_NODE; in acpi_parse_eio_master()
/linux/arch/loongarch/kvm/
H A DMakefile20 kvm-y += intc/eiointc.o
H A Dvm.c211 return (kvm->arch.ipi && kvm->arch.eiointc && kvm->arch.pch_pic); in kvm_arch_irqchip_in_kernel()
H A Dmain.c412 /* Register LoongArch EIOINTC interrupt controller interface. */ in kvm_loongarch_env_init()