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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dsamsung,pinctrl-wakeup-interrupt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC pin controller - wake-up interrupt controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
18 External wake-up interrupts for Samsung S3C/S5P/Exynos SoC pin controller.
19 For S3C24xx, S3C64xx, S5PV210 and Exynos4210 compatible wake-up interrupt
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H A Dmediatek,mt6878-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6878-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Igor Belwon <igor.belwon@mentallysanemainliners.org>
18 const: mediatek,mt6878-pinctrl
22 - description: pin controller base
23 - description: bl group IO
24 - description: bm group IO
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H A Dmediatek,mt6795-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Sean Wang <sean.wang@kernel.org>
14 The MediaTek's MT6795 Pin controller is used to control SoC pins.
18 const: mediatek,mt6795-pinctrl
20 gpio-controller: true
22 '#gpio-cells':
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H A Dmediatek,mt6779-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Teng <andy.teng@mediatek.com>
11 - Sean Wang <sean.wang@kernel.org>
20 - mediatek,mt6779-pinctrl
21 - mediatek,mt6797-pinctrl
24 description: Physical addresses for GPIO base(s) and EINT registers.
26 reg-names: true
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H A Dmediatek,mt6893-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6893-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
13 The MediaTek's MT6893 Pin controller is used to control SoC pins.
17 const: mediatek,mt6893-pinctrl
21 - description: pin controller base
22 - description: rm group IO
23 - description: bm group IO
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H A Dmediatek,mt8188-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hui Liu <hui.liu@mediatek.com>
13 The MediaTek's MT8188 Pin controller is used to control SoC pins.
17 const: mediatek,mt8188-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
25 are defined in <dt-bindings/gpio/gpio.h>.
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H A Dsamsung,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
22 - External GPIO interrupts (see interrupts property in pin controller node);
24 - External wake-up interrupts - multiplexed (capable of waking up the system
25 see interrupts property in external wake-up interrupt controller node -
26 samsung,pinctrl-wakeup-interrupt.yaml);
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H A Dmediatek,mt8186-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
13 The MediaTek's MT8186 Pin controller is used to control SoC pins.
17 const: mediatek,mt8186-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
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H A Dmediatek,mt7986-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
13 The MediaTek's MT7986 Pin controller is used to control SoC pins.
18 - mediatek,mt7986a-pinctrl
19 - mediatek,mt7986b-pinctrl
25 reg-names:
27 - const: gpio
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H A Dmediatek,mt7981-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7981-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Golle <daniel@makrotopia.org>
13 The MediaTek's MT7981 Pin controller is used to control SoC pins.
18 - mediatek,mt7981-pinctrl
24 reg-names:
26 - const: gpio
27 - const: iocfg_rt
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H A Dmediatek,mt8192-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
13 The MediaTek's MT8192 Pin controller is used to control SoC pins.
17 const: mediatek,mt8192-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
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H A Dmediatek,mt7988-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7988-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
13 The MediaTek's MT7988 Pin controller is used to control SoC pins.
18 - mediatek,mt7988-pinctrl
24 reg-names:
26 - const: gpio
27 - const: iocfg_tr
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H A Dmediatek,mt8195-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
13 The MediaTek's MT8195 Pin controller is used to control SoC pins.
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
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/linux/drivers/pinctrl/mediatek/
H A Dmtk-eint.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2014-2025 MediaTek Inc.
24 #include "mtk-eint.h"
74 static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint, in mtk_eint_get_offset() argument
78 unsigned int idx = eint->pins[eint_num].index; in mtk_eint_get_offset()
79 unsigned int inst = eint->pins[eint_num].instance; in mtk_eint_get_offset()
82 reg = eint->base[inst] + offset + (idx / 32 * 4); in mtk_eint_get_offset()
87 static unsigned int mtk_eint_can_en_debounce(struct mtk_eint *eint, in mtk_eint_can_en_debounce() argument
91 unsigned int bit = BIT(eint->pins[eint_num].index % 32); in mtk_eint_can_en_debounce()
92 void __iomem *reg = mtk_eint_get_offset(eint, eint_num, in mtk_eint_can_en_debounce()
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H A Dpinctrl-mtk-common-v2.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/pinctrl/mt65xx.h>
19 #include "mtk-eint.h"
20 #include "pinctrl-mtk-common-v2.h"
23 * struct mtk_drive_desc - the structure that holds the information
30 * formula: output = ((input) / step - 1) * scal
50 writel_relaxed(val, pctl->base[i] + reg); in mtk_w32()
55 return readl_relaxed(pctl->base[i] + reg); in mtk_r32()
63 spin_lock_irqsave(&pctl->lock, flags); in mtk_rmw()
70 spin_unlock_irqrestore(&pctl->lock, flags); in mtk_rmw()
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/linux/drivers/pinctrl/samsung/
H A Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
70 * enum pud_index - Possible index values to access the pud_val array.
84 * enum eint_type - possible external interrupt types.
104 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
135 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
137 * @pctl_offset: starting offset of the pin-bank registers.
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H A Dpinctrl-exynos-arm.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
49 unsigned int *pud_val = drvdata->pud_val; in s5pv210_pud_value_init()
58 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
75 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in s5pv210_retention_init()
77 return ERR_PTR(-ENOMEM); in s5pv210_retention_init()
79 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); in s5pv210_retention_init()
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H A Dpinctrl-exynos.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
29 #include <linux/soc/samsung/exynos-pmu.h>
30 #include <linux/soc/samsung/exynos-regs-pmu.h>
32 #include "pinctrl-samsung.h"
33 #include "pinctrl-exynos.h"
67 if (bank->eint_mask_offset) in exynos_irq_mask()
68 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_mask()
70 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
72 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_mask()
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/linux/sound/soc/codecs/
H A Dmt6359-accdet.c1 // SPDX-License-Identifier: GPL-2.0
3 // mt6359-accdet.c -- ALSA SoC mt6359 accdet driver
27 #include "mt6359-accdet.h"
31 #define REGISTER_VAL(x) ((x) - 1)
73 if (priv->data->eint_detect_mode == 0x3 || in adjust_eint_analog_setting()
74 priv->data->eint_detect_mode == 0x4) { in adjust_eint_analog_setting()
76 regmap_update_bits(priv->regmap, in adjust_eint_analog_setting()
79 if (priv->data->eint_detect_mode == 0x4) { in adjust_eint_analog_setting()
80 if (priv->caps & ACCDET_PMIC_EINT0) { in adjust_eint_analog_setting()
82 regmap_update_bits(priv->regmap, in adjust_eint_analog_setting()
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/linux/arch/sparc/include/asm/
H A Decc.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
22 * ----------------------------------------
24 * ----------------------------------------
40 * -----------------------------
41 * | RESV | ECHECK | EINT |
42 * -----------------------------
46 * EINT: Enable Interrupts for correctable errors. 0=off 1=on
53 * -----------------------------------------------------
54 * | MID | S | RSV | VA | BM |AT| C| SZ |TYP| PADDR |
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/linux/arch/arm/boot/dts/samsung/
H A Ds3c64xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S3C64xx SoC series common device tree source
7 * Samsung's S3C64xx SoC series device nodes are listed in this file.
16 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,arm1176jzf-s";
43 compatible = "simple-bus";
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H A Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC device tree source
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
10 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
20 #include "exynos4-cpu-thermal.dtsi"
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
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/linux/arch/arm/mach-s3c/
H A Dmach-crag6410.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/input-event-codes.h>
33 #include <linux/platform_data/s3c-hsotg.h>
43 #include <asm/mach-types.h>
47 #include "regs-gpio.h"
48 #include "gpio-samsung.h"
53 #include "gpio-cfg.h"
54 #include <linux/platform_data/spi-s3c64xx.h>
59 #include <linux/platform_data/i2c-s3c2410.h>
64 #include "regs-gpio-memport-s3c64xx.h"
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H A Ds3c64xx.c1 // SPDX-License-Identifier: GPL-2.0
29 #include <linux/dma-mapping.h>
31 #include <linux/irqchip/arm-vic.h>
40 #include "regs-gpio.h"
41 #include "gpio-samsung.h"
46 #include "gpio-cfg.h"
47 #include "pwm-core.h"
48 #include "regs-irqtype.h"
50 #include "irq-uart-s3c64xx.h"
70 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); in s3c64xx_init_uarts()
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/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov9.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAuto v9 SoC device tree source
9 #include <dt-bindings/clock/samsung,exynosautov9.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,boot-mode.h>
12 #include <dt-bindings/soc/samsung,exynos-usi.h>
16 #address-cells = <2>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
31 arm-pmu {
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