1e46df235SSean Wang // SPDX-License-Identifier: GPL-2.0
2e46df235SSean Wang // Copyright (c) 2014-2018 MediaTek Inc.
3e46df235SSean Wang
4e46df235SSean Wang /*
5e46df235SSean Wang * Library for MediaTek External Interrupt Support
6e46df235SSean Wang *
7e46df235SSean Wang * Author: Maoguang Meng <maoguang.meng@mediatek.com>
8e46df235SSean Wang * Sean Wang <sean.wang@mediatek.com>
9e46df235SSean Wang *
10e46df235SSean Wang */
11e46df235SSean Wang
12e46df235SSean Wang #include <linux/delay.h>
13e46df235SSean Wang #include <linux/err.h>
141c5fb66aSLinus Walleij #include <linux/gpio/driver.h>
15e46df235SSean Wang #include <linux/io.h>
16a8cfcf15SArnd Bergmann #include <linux/irqchip/chained_irq.h>
17e46df235SSean Wang #include <linux/irqdomain.h>
188174a851SLight Hsieh #include <linux/module.h>
19e46df235SSean Wang #include <linux/of_irq.h>
20e46df235SSean Wang #include <linux/platform_device.h>
21e46df235SSean Wang
22e46df235SSean Wang #include "mtk-eint.h"
23e46df235SSean Wang
24e46df235SSean Wang #define MTK_EINT_EDGE_SENSITIVE 0
25e46df235SSean Wang #define MTK_EINT_LEVEL_SENSITIVE 1
26e46df235SSean Wang #define MTK_EINT_DBNC_SET_DBNC_BITS 4
27e1ff91f9SAngeloGioacchino Del Regno #define MTK_EINT_DBNC_MAX 16
28e46df235SSean Wang #define MTK_EINT_DBNC_RST_BIT (0x1 << 1)
29e46df235SSean Wang #define MTK_EINT_DBNC_SET_EN (0x1 << 0)
30e46df235SSean Wang
31e46df235SSean Wang static const struct mtk_eint_regs mtk_generic_eint_regs = {
32e46df235SSean Wang .stat = 0x000,
33e46df235SSean Wang .ack = 0x040,
34e46df235SSean Wang .mask = 0x080,
35e46df235SSean Wang .mask_set = 0x0c0,
36e46df235SSean Wang .mask_clr = 0x100,
37e46df235SSean Wang .sens = 0x140,
38e46df235SSean Wang .sens_set = 0x180,
39e46df235SSean Wang .sens_clr = 0x1c0,
40e46df235SSean Wang .soft = 0x200,
41e46df235SSean Wang .soft_set = 0x240,
42e46df235SSean Wang .soft_clr = 0x280,
43e46df235SSean Wang .pol = 0x300,
44e46df235SSean Wang .pol_set = 0x340,
45e46df235SSean Wang .pol_clr = 0x380,
46e46df235SSean Wang .dom_en = 0x400,
47e46df235SSean Wang .dbnc_ctrl = 0x500,
48e46df235SSean Wang .dbnc_set = 0x600,
49e46df235SSean Wang .dbnc_clr = 0x700,
50e46df235SSean Wang };
51e46df235SSean Wang
52e1ff91f9SAngeloGioacchino Del Regno const unsigned int debounce_time_mt2701[] = {
53e1ff91f9SAngeloGioacchino Del Regno 500, 1000, 16000, 32000, 64000, 128000, 256000, 0
54e1ff91f9SAngeloGioacchino Del Regno };
552e35b25dSLinus Walleij EXPORT_SYMBOL_GPL(debounce_time_mt2701);
56e1ff91f9SAngeloGioacchino Del Regno
57e1ff91f9SAngeloGioacchino Del Regno const unsigned int debounce_time_mt6765[] = {
58e1ff91f9SAngeloGioacchino Del Regno 125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
59e1ff91f9SAngeloGioacchino Del Regno };
602e35b25dSLinus Walleij EXPORT_SYMBOL_GPL(debounce_time_mt6765);
61e1ff91f9SAngeloGioacchino Del Regno
62e1ff91f9SAngeloGioacchino Del Regno const unsigned int debounce_time_mt6795[] = {
63e1ff91f9SAngeloGioacchino Del Regno 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
64e1ff91f9SAngeloGioacchino Del Regno };
652e35b25dSLinus Walleij EXPORT_SYMBOL_GPL(debounce_time_mt6795);
66e1ff91f9SAngeloGioacchino Del Regno
mtk_eint_get_offset(struct mtk_eint * eint,unsigned int eint_num,unsigned int offset)67e46df235SSean Wang static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
68e46df235SSean Wang unsigned int eint_num,
69e46df235SSean Wang unsigned int offset)
70e46df235SSean Wang {
71e46df235SSean Wang unsigned int eint_base = 0;
72e46df235SSean Wang void __iomem *reg;
73e46df235SSean Wang
74e46df235SSean Wang if (eint_num >= eint->hw->ap_num)
75e46df235SSean Wang eint_base = eint->hw->ap_num;
76e46df235SSean Wang
77e46df235SSean Wang reg = eint->base + offset + ((eint_num - eint_base) / 32) * 4;
78e46df235SSean Wang
79e46df235SSean Wang return reg;
80e46df235SSean Wang }
81e46df235SSean Wang
mtk_eint_can_en_debounce(struct mtk_eint * eint,unsigned int eint_num)82e46df235SSean Wang static unsigned int mtk_eint_can_en_debounce(struct mtk_eint *eint,
83e46df235SSean Wang unsigned int eint_num)
84e46df235SSean Wang {
85e46df235SSean Wang unsigned int sens;
86e46df235SSean Wang unsigned int bit = BIT(eint_num % 32);
87e46df235SSean Wang void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
88e46df235SSean Wang eint->regs->sens);
89e46df235SSean Wang
90e46df235SSean Wang if (readl(reg) & bit)
91e46df235SSean Wang sens = MTK_EINT_LEVEL_SENSITIVE;
92e46df235SSean Wang else
93e46df235SSean Wang sens = MTK_EINT_EDGE_SENSITIVE;
94e46df235SSean Wang
95e46df235SSean Wang if (eint_num < eint->hw->db_cnt && sens != MTK_EINT_EDGE_SENSITIVE)
96e46df235SSean Wang return 1;
97e46df235SSean Wang else
98e46df235SSean Wang return 0;
99e46df235SSean Wang }
100e46df235SSean Wang
mtk_eint_flip_edge(struct mtk_eint * eint,int hwirq)101e46df235SSean Wang static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq)
102e46df235SSean Wang {
103e46df235SSean Wang int start_level, curr_level;
104e46df235SSean Wang unsigned int reg_offset;
105e46df235SSean Wang u32 mask = BIT(hwirq & 0x1f);
106e46df235SSean Wang u32 port = (hwirq >> 5) & eint->hw->port_mask;
107e46df235SSean Wang void __iomem *reg = eint->base + (port << 2);
108e46df235SSean Wang
109e46df235SSean Wang curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq);
110e46df235SSean Wang
111e46df235SSean Wang do {
112e46df235SSean Wang start_level = curr_level;
113e46df235SSean Wang if (start_level)
114e46df235SSean Wang reg_offset = eint->regs->pol_clr;
115e46df235SSean Wang else
116e46df235SSean Wang reg_offset = eint->regs->pol_set;
117e46df235SSean Wang writel(mask, reg + reg_offset);
118e46df235SSean Wang
119e46df235SSean Wang curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl,
120e46df235SSean Wang hwirq);
121e46df235SSean Wang } while (start_level != curr_level);
122e46df235SSean Wang
123e46df235SSean Wang return start_level;
124e46df235SSean Wang }
125e46df235SSean Wang
mtk_eint_mask(struct irq_data * d)126e46df235SSean Wang static void mtk_eint_mask(struct irq_data *d)
127e46df235SSean Wang {
128e46df235SSean Wang struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
129e46df235SSean Wang u32 mask = BIT(d->hwirq & 0x1f);
130e46df235SSean Wang void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
131e46df235SSean Wang eint->regs->mask_set);
132e46df235SSean Wang
1339d957a95SNicolas Boichat eint->cur_mask[d->hwirq >> 5] &= ~mask;
1349d957a95SNicolas Boichat
135e46df235SSean Wang writel(mask, reg);
136e46df235SSean Wang }
137e46df235SSean Wang
mtk_eint_unmask(struct irq_data * d)138e46df235SSean Wang static void mtk_eint_unmask(struct irq_data *d)
139e46df235SSean Wang {
140e46df235SSean Wang struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
141e46df235SSean Wang u32 mask = BIT(d->hwirq & 0x1f);
142e46df235SSean Wang void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
143e46df235SSean Wang eint->regs->mask_clr);
144e46df235SSean Wang
1459d957a95SNicolas Boichat eint->cur_mask[d->hwirq >> 5] |= mask;
1469d957a95SNicolas Boichat
147e46df235SSean Wang writel(mask, reg);
148e46df235SSean Wang
149e46df235SSean Wang if (eint->dual_edge[d->hwirq])
150e46df235SSean Wang mtk_eint_flip_edge(eint, d->hwirq);
151e46df235SSean Wang }
152e46df235SSean Wang
mtk_eint_get_mask(struct mtk_eint * eint,unsigned int eint_num)153e46df235SSean Wang static unsigned int mtk_eint_get_mask(struct mtk_eint *eint,
154e46df235SSean Wang unsigned int eint_num)
155e46df235SSean Wang {
156e46df235SSean Wang unsigned int bit = BIT(eint_num % 32);
157e46df235SSean Wang void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
158e46df235SSean Wang eint->regs->mask);
159e46df235SSean Wang
160e46df235SSean Wang return !!(readl(reg) & bit);
161e46df235SSean Wang }
162e46df235SSean Wang
mtk_eint_ack(struct irq_data * d)163e46df235SSean Wang static void mtk_eint_ack(struct irq_data *d)
164e46df235SSean Wang {
165e46df235SSean Wang struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
166e46df235SSean Wang u32 mask = BIT(d->hwirq & 0x1f);
167e46df235SSean Wang void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
168e46df235SSean Wang eint->regs->ack);
169e46df235SSean Wang
170e46df235SSean Wang writel(mask, reg);
171e46df235SSean Wang }
172e46df235SSean Wang
mtk_eint_set_type(struct irq_data * d,unsigned int type)173e46df235SSean Wang static int mtk_eint_set_type(struct irq_data *d, unsigned int type)
174e46df235SSean Wang {
175e46df235SSean Wang struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
176b40b760aSHailong Fan bool masked;
177e46df235SSean Wang u32 mask = BIT(d->hwirq & 0x1f);
178e46df235SSean Wang void __iomem *reg;
179e46df235SSean Wang
180e46df235SSean Wang if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
181e46df235SSean Wang ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
182e46df235SSean Wang dev_err(eint->dev,
183e46df235SSean Wang "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
184e46df235SSean Wang d->irq, d->hwirq, type);
185e46df235SSean Wang return -EINVAL;
186e46df235SSean Wang }
187e46df235SSean Wang
188e46df235SSean Wang if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
189e46df235SSean Wang eint->dual_edge[d->hwirq] = 1;
190e46df235SSean Wang else
191e46df235SSean Wang eint->dual_edge[d->hwirq] = 0;
192e46df235SSean Wang
193b40b760aSHailong Fan if (!mtk_eint_get_mask(eint, d->hwirq)) {
194b40b760aSHailong Fan mtk_eint_mask(d);
195b40b760aSHailong Fan masked = false;
196b40b760aSHailong Fan } else {
197b40b760aSHailong Fan masked = true;
198b40b760aSHailong Fan }
199b40b760aSHailong Fan
200e46df235SSean Wang if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
201e46df235SSean Wang reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr);
202e46df235SSean Wang writel(mask, reg);
203e46df235SSean Wang } else {
204e46df235SSean Wang reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_set);
205e46df235SSean Wang writel(mask, reg);
206e46df235SSean Wang }
207e46df235SSean Wang
208e46df235SSean Wang if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
209e46df235SSean Wang reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr);
210e46df235SSean Wang writel(mask, reg);
211e46df235SSean Wang } else {
212e46df235SSean Wang reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_set);
213e46df235SSean Wang writel(mask, reg);
214e46df235SSean Wang }
215e46df235SSean Wang
216b40b760aSHailong Fan mtk_eint_ack(d);
217b40b760aSHailong Fan if (!masked)
218b40b760aSHailong Fan mtk_eint_unmask(d);
219e46df235SSean Wang
220e46df235SSean Wang return 0;
221e46df235SSean Wang }
222e46df235SSean Wang
mtk_eint_irq_set_wake(struct irq_data * d,unsigned int on)223e46df235SSean Wang static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
224e46df235SSean Wang {
225e46df235SSean Wang struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
226e46df235SSean Wang int shift = d->hwirq & 0x1f;
227e46df235SSean Wang int reg = d->hwirq >> 5;
228e46df235SSean Wang
229e46df235SSean Wang if (on)
230e46df235SSean Wang eint->wake_mask[reg] |= BIT(shift);
231e46df235SSean Wang else
232e46df235SSean Wang eint->wake_mask[reg] &= ~BIT(shift);
233e46df235SSean Wang
234e46df235SSean Wang return 0;
235e46df235SSean Wang }
236e46df235SSean Wang
mtk_eint_chip_write_mask(const struct mtk_eint * eint,void __iomem * base,u32 * buf)237e46df235SSean Wang static void mtk_eint_chip_write_mask(const struct mtk_eint *eint,
238e46df235SSean Wang void __iomem *base, u32 *buf)
239e46df235SSean Wang {
240e46df235SSean Wang int port;
241e46df235SSean Wang void __iomem *reg;
242e46df235SSean Wang
243e46df235SSean Wang for (port = 0; port < eint->hw->ports; port++) {
244e46df235SSean Wang reg = base + (port << 2);
245e46df235SSean Wang writel_relaxed(~buf[port], reg + eint->regs->mask_set);
246e46df235SSean Wang writel_relaxed(buf[port], reg + eint->regs->mask_clr);
247e46df235SSean Wang }
248e46df235SSean Wang }
249e46df235SSean Wang
mtk_eint_irq_request_resources(struct irq_data * d)250e46df235SSean Wang static int mtk_eint_irq_request_resources(struct irq_data *d)
251e46df235SSean Wang {
252e46df235SSean Wang struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
253e46df235SSean Wang struct gpio_chip *gpio_c;
254e46df235SSean Wang unsigned int gpio_n;
255e46df235SSean Wang int err;
256e46df235SSean Wang
257e46df235SSean Wang err = eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq,
258e46df235SSean Wang &gpio_n, &gpio_c);
259e46df235SSean Wang if (err < 0) {
260e46df235SSean Wang dev_err(eint->dev, "Can not find pin\n");
261e46df235SSean Wang return err;
262e46df235SSean Wang }
263e46df235SSean Wang
264e46df235SSean Wang err = gpiochip_lock_as_irq(gpio_c, gpio_n);
265e46df235SSean Wang if (err < 0) {
266e46df235SSean Wang dev_err(eint->dev, "unable to lock HW IRQ %lu for IRQ\n",
267e46df235SSean Wang irqd_to_hwirq(d));
268e46df235SSean Wang return err;
269e46df235SSean Wang }
270e46df235SSean Wang
271e46df235SSean Wang err = eint->gpio_xlate->set_gpio_as_eint(eint->pctl, d->hwirq);
272e46df235SSean Wang if (err < 0) {
273e46df235SSean Wang dev_err(eint->dev, "Can not eint mode\n");
274e46df235SSean Wang return err;
275e46df235SSean Wang }
276e46df235SSean Wang
277e46df235SSean Wang return 0;
278e46df235SSean Wang }
279e46df235SSean Wang
mtk_eint_irq_release_resources(struct irq_data * d)280e46df235SSean Wang static void mtk_eint_irq_release_resources(struct irq_data *d)
281e46df235SSean Wang {
282e46df235SSean Wang struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
283e46df235SSean Wang struct gpio_chip *gpio_c;
284e46df235SSean Wang unsigned int gpio_n;
285e46df235SSean Wang
286e46df235SSean Wang eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, &gpio_n,
287e46df235SSean Wang &gpio_c);
288e46df235SSean Wang
289e46df235SSean Wang gpiochip_unlock_as_irq(gpio_c, gpio_n);
290e46df235SSean Wang }
291e46df235SSean Wang
292e46df235SSean Wang static struct irq_chip mtk_eint_irq_chip = {
293e46df235SSean Wang .name = "mt-eint",
294e46df235SSean Wang .irq_disable = mtk_eint_mask,
295e46df235SSean Wang .irq_mask = mtk_eint_mask,
296e46df235SSean Wang .irq_unmask = mtk_eint_unmask,
297e46df235SSean Wang .irq_ack = mtk_eint_ack,
298e46df235SSean Wang .irq_set_type = mtk_eint_set_type,
299e46df235SSean Wang .irq_set_wake = mtk_eint_irq_set_wake,
300e46df235SSean Wang .irq_request_resources = mtk_eint_irq_request_resources,
301e46df235SSean Wang .irq_release_resources = mtk_eint_irq_release_resources,
302e46df235SSean Wang };
303e46df235SSean Wang
mtk_eint_hw_init(struct mtk_eint * eint)304e46df235SSean Wang static unsigned int mtk_eint_hw_init(struct mtk_eint *eint)
305e46df235SSean Wang {
306*11780e37SRicardo Ribalda void __iomem *dom_en = eint->base + eint->regs->dom_en;
307*11780e37SRicardo Ribalda void __iomem *mask_set = eint->base + eint->regs->mask_set;
308e46df235SSean Wang unsigned int i;
309e46df235SSean Wang
310e46df235SSean Wang for (i = 0; i < eint->hw->ap_num; i += 32) {
311*11780e37SRicardo Ribalda writel(0xffffffff, dom_en);
312*11780e37SRicardo Ribalda writel(0xffffffff, mask_set);
313*11780e37SRicardo Ribalda dom_en += 4;
314*11780e37SRicardo Ribalda mask_set += 4;
315e46df235SSean Wang }
316e46df235SSean Wang
317e46df235SSean Wang return 0;
318e46df235SSean Wang }
319e46df235SSean Wang
320e46df235SSean Wang static inline void
mtk_eint_debounce_process(struct mtk_eint * eint,int index)321e46df235SSean Wang mtk_eint_debounce_process(struct mtk_eint *eint, int index)
322e46df235SSean Wang {
323e46df235SSean Wang unsigned int rst, ctrl_offset;
324e46df235SSean Wang unsigned int bit, dbnc;
325e46df235SSean Wang
326e46df235SSean Wang ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_ctrl;
327e46df235SSean Wang dbnc = readl(eint->base + ctrl_offset);
328e46df235SSean Wang bit = MTK_EINT_DBNC_SET_EN << ((index % 4) * 8);
329e46df235SSean Wang if ((bit & dbnc) > 0) {
330e46df235SSean Wang ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_set;
331e46df235SSean Wang rst = MTK_EINT_DBNC_RST_BIT << ((index % 4) * 8);
332e46df235SSean Wang writel(rst, eint->base + ctrl_offset);
333e46df235SSean Wang }
334e46df235SSean Wang }
335e46df235SSean Wang
mtk_eint_irq_handler(struct irq_desc * desc)336e46df235SSean Wang static void mtk_eint_irq_handler(struct irq_desc *desc)
337e46df235SSean Wang {
338e46df235SSean Wang struct irq_chip *chip = irq_desc_get_chip(desc);
339e46df235SSean Wang struct mtk_eint *eint = irq_desc_get_handler_data(desc);
340e46df235SSean Wang unsigned int status, eint_num;
341a9cb09b7SMarc Zyngier int offset, mask_offset, index;
342e46df235SSean Wang void __iomem *reg = mtk_eint_get_offset(eint, 0, eint->regs->stat);
343e46df235SSean Wang int dual_edge, start_level, curr_level;
344e46df235SSean Wang
345e46df235SSean Wang chained_irq_enter(chip, desc);
346e46df235SSean Wang for (eint_num = 0; eint_num < eint->hw->ap_num; eint_num += 32,
347e46df235SSean Wang reg += 4) {
348e46df235SSean Wang status = readl(reg);
349e46df235SSean Wang while (status) {
350e46df235SSean Wang offset = __ffs(status);
35135594bc7SNicolas Boichat mask_offset = eint_num >> 5;
352e46df235SSean Wang index = eint_num + offset;
353e46df235SSean Wang status &= ~BIT(offset);
354e46df235SSean Wang
35535594bc7SNicolas Boichat /*
35635594bc7SNicolas Boichat * If we get an interrupt on pin that was only required
35735594bc7SNicolas Boichat * for wake (but no real interrupt requested), mask the
35835594bc7SNicolas Boichat * interrupt (as would mtk_eint_resume do anyway later
35935594bc7SNicolas Boichat * in the resume sequence).
36035594bc7SNicolas Boichat */
36135594bc7SNicolas Boichat if (eint->wake_mask[mask_offset] & BIT(offset) &&
36235594bc7SNicolas Boichat !(eint->cur_mask[mask_offset] & BIT(offset))) {
36335594bc7SNicolas Boichat writel_relaxed(BIT(offset), reg -
36435594bc7SNicolas Boichat eint->regs->stat +
36535594bc7SNicolas Boichat eint->regs->mask_set);
36635594bc7SNicolas Boichat }
36735594bc7SNicolas Boichat
368e46df235SSean Wang dual_edge = eint->dual_edge[index];
369e46df235SSean Wang if (dual_edge) {
370e46df235SSean Wang /*
371e46df235SSean Wang * Clear soft-irq in case we raised it last
372e46df235SSean Wang * time.
373e46df235SSean Wang */
374e46df235SSean Wang writel(BIT(offset), reg - eint->regs->stat +
375e46df235SSean Wang eint->regs->soft_clr);
376e46df235SSean Wang
377e46df235SSean Wang start_level =
378e46df235SSean Wang eint->gpio_xlate->get_gpio_state(eint->pctl,
379e46df235SSean Wang index);
380e46df235SSean Wang }
381e46df235SSean Wang
382a9cb09b7SMarc Zyngier generic_handle_domain_irq(eint->domain, index);
383e46df235SSean Wang
384e46df235SSean Wang if (dual_edge) {
385e46df235SSean Wang curr_level = mtk_eint_flip_edge(eint, index);
386e46df235SSean Wang
387e46df235SSean Wang /*
388e46df235SSean Wang * If level changed, we might lost one edge
389e46df235SSean Wang * interrupt, raised it through soft-irq.
390e46df235SSean Wang */
391e46df235SSean Wang if (start_level != curr_level)
392e46df235SSean Wang writel(BIT(offset), reg -
393e46df235SSean Wang eint->regs->stat +
394e46df235SSean Wang eint->regs->soft_set);
395e46df235SSean Wang }
396e46df235SSean Wang
397e46df235SSean Wang if (index < eint->hw->db_cnt)
398e46df235SSean Wang mtk_eint_debounce_process(eint, index);
399e46df235SSean Wang }
400e46df235SSean Wang }
401e46df235SSean Wang chained_irq_exit(chip, desc);
402e46df235SSean Wang }
403e46df235SSean Wang
mtk_eint_do_suspend(struct mtk_eint * eint)404e46df235SSean Wang int mtk_eint_do_suspend(struct mtk_eint *eint)
405e46df235SSean Wang {
406e46df235SSean Wang mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask);
407e46df235SSean Wang
408e46df235SSean Wang return 0;
409e46df235SSean Wang }
4108174a851SLight Hsieh EXPORT_SYMBOL_GPL(mtk_eint_do_suspend);
411e46df235SSean Wang
mtk_eint_do_resume(struct mtk_eint * eint)412e46df235SSean Wang int mtk_eint_do_resume(struct mtk_eint *eint)
413e46df235SSean Wang {
414e46df235SSean Wang mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask);
415e46df235SSean Wang
416e46df235SSean Wang return 0;
417e46df235SSean Wang }
4188174a851SLight Hsieh EXPORT_SYMBOL_GPL(mtk_eint_do_resume);
419e46df235SSean Wang
mtk_eint_set_debounce(struct mtk_eint * eint,unsigned long eint_num,unsigned int debounce)420e46df235SSean Wang int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num,
421e46df235SSean Wang unsigned int debounce)
422e46df235SSean Wang {
423e46df235SSean Wang int virq, eint_offset;
424e46df235SSean Wang unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask,
425e46df235SSean Wang dbnc;
426e46df235SSean Wang struct irq_data *d;
427e46df235SSean Wang
428e1ff91f9SAngeloGioacchino Del Regno if (!eint->hw->db_time)
429e1ff91f9SAngeloGioacchino Del Regno return -EOPNOTSUPP;
430e1ff91f9SAngeloGioacchino Del Regno
431e46df235SSean Wang virq = irq_find_mapping(eint->domain, eint_num);
432e46df235SSean Wang eint_offset = (eint_num % 4) * 8;
433e46df235SSean Wang d = irq_get_irq_data(virq);
434e46df235SSean Wang
435e46df235SSean Wang set_offset = (eint_num / 4) * 4 + eint->regs->dbnc_set;
436e46df235SSean Wang clr_offset = (eint_num / 4) * 4 + eint->regs->dbnc_clr;
437e46df235SSean Wang
438e46df235SSean Wang if (!mtk_eint_can_en_debounce(eint, eint_num))
439e46df235SSean Wang return -EINVAL;
440e46df235SSean Wang
441e1ff91f9SAngeloGioacchino Del Regno dbnc = eint->num_db_time;
442e1ff91f9SAngeloGioacchino Del Regno for (i = 0; i < eint->num_db_time; i++) {
443e1ff91f9SAngeloGioacchino Del Regno if (debounce <= eint->hw->db_time[i]) {
444e46df235SSean Wang dbnc = i;
445e46df235SSean Wang break;
446e46df235SSean Wang }
447e46df235SSean Wang }
448e46df235SSean Wang
449e46df235SSean Wang if (!mtk_eint_get_mask(eint, eint_num)) {
450e46df235SSean Wang mtk_eint_mask(d);
451e46df235SSean Wang unmask = 1;
452e46df235SSean Wang } else {
453e46df235SSean Wang unmask = 0;
454e46df235SSean Wang }
455e46df235SSean Wang
456e46df235SSean Wang clr_bit = 0xff << eint_offset;
457e46df235SSean Wang writel(clr_bit, eint->base + clr_offset);
458e46df235SSean Wang
459e46df235SSean Wang bit = ((dbnc << MTK_EINT_DBNC_SET_DBNC_BITS) | MTK_EINT_DBNC_SET_EN) <<
460e46df235SSean Wang eint_offset;
461e46df235SSean Wang rst = MTK_EINT_DBNC_RST_BIT << eint_offset;
462e46df235SSean Wang writel(rst | bit, eint->base + set_offset);
463e46df235SSean Wang
464e46df235SSean Wang /*
465e46df235SSean Wang * Delay a while (more than 2T) to wait for hw debounce counter reset
466e46df235SSean Wang * work correctly.
467e46df235SSean Wang */
468e46df235SSean Wang udelay(1);
469e46df235SSean Wang if (unmask == 1)
470e46df235SSean Wang mtk_eint_unmask(d);
471e46df235SSean Wang
472e46df235SSean Wang return 0;
473e46df235SSean Wang }
4748174a851SLight Hsieh EXPORT_SYMBOL_GPL(mtk_eint_set_debounce);
475e46df235SSean Wang
mtk_eint_find_irq(struct mtk_eint * eint,unsigned long eint_n)476e46df235SSean Wang int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
477e46df235SSean Wang {
478e46df235SSean Wang int irq;
479e46df235SSean Wang
480e46df235SSean Wang irq = irq_find_mapping(eint->domain, eint_n);
481e46df235SSean Wang if (!irq)
482e46df235SSean Wang return -EINVAL;
483e46df235SSean Wang
484e46df235SSean Wang return irq;
485e46df235SSean Wang }
4868174a851SLight Hsieh EXPORT_SYMBOL_GPL(mtk_eint_find_irq);
487e46df235SSean Wang
mtk_eint_do_init(struct mtk_eint * eint)488e46df235SSean Wang int mtk_eint_do_init(struct mtk_eint *eint)
489e46df235SSean Wang {
490e46df235SSean Wang int i;
491e46df235SSean Wang
492e46df235SSean Wang /* If clients don't assign a specific regs, let's use generic one */
493e46df235SSean Wang if (!eint->regs)
494e46df235SSean Wang eint->regs = &mtk_generic_eint_regs;
495e46df235SSean Wang
496e46df235SSean Wang eint->wake_mask = devm_kcalloc(eint->dev, eint->hw->ports,
497e46df235SSean Wang sizeof(*eint->wake_mask), GFP_KERNEL);
498e46df235SSean Wang if (!eint->wake_mask)
499e46df235SSean Wang return -ENOMEM;
500e46df235SSean Wang
501e46df235SSean Wang eint->cur_mask = devm_kcalloc(eint->dev, eint->hw->ports,
502e46df235SSean Wang sizeof(*eint->cur_mask), GFP_KERNEL);
503e46df235SSean Wang if (!eint->cur_mask)
504e46df235SSean Wang return -ENOMEM;
505e46df235SSean Wang
506e46df235SSean Wang eint->dual_edge = devm_kcalloc(eint->dev, eint->hw->ap_num,
507e46df235SSean Wang sizeof(int), GFP_KERNEL);
508e46df235SSean Wang if (!eint->dual_edge)
509e46df235SSean Wang return -ENOMEM;
510e46df235SSean Wang
511e46df235SSean Wang eint->domain = irq_domain_add_linear(eint->dev->of_node,
512e46df235SSean Wang eint->hw->ap_num,
513e46df235SSean Wang &irq_domain_simple_ops, NULL);
514e46df235SSean Wang if (!eint->domain)
515e46df235SSean Wang return -ENOMEM;
516e46df235SSean Wang
517e1ff91f9SAngeloGioacchino Del Regno if (eint->hw->db_time) {
518e1ff91f9SAngeloGioacchino Del Regno for (i = 0; i < MTK_EINT_DBNC_MAX; i++)
519e1ff91f9SAngeloGioacchino Del Regno if (eint->hw->db_time[i] == 0)
520e1ff91f9SAngeloGioacchino Del Regno break;
521e1ff91f9SAngeloGioacchino Del Regno eint->num_db_time = i;
522e1ff91f9SAngeloGioacchino Del Regno }
523e1ff91f9SAngeloGioacchino Del Regno
524e46df235SSean Wang mtk_eint_hw_init(eint);
525e46df235SSean Wang for (i = 0; i < eint->hw->ap_num; i++) {
526e46df235SSean Wang int virq = irq_create_mapping(eint->domain, i);
527e46df235SSean Wang
528e46df235SSean Wang irq_set_chip_and_handler(virq, &mtk_eint_irq_chip,
529e46df235SSean Wang handle_level_irq);
530e46df235SSean Wang irq_set_chip_data(virq, eint);
531e46df235SSean Wang }
532e46df235SSean Wang
533e46df235SSean Wang irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler,
534e46df235SSean Wang eint);
535e46df235SSean Wang
536e46df235SSean Wang return 0;
537e46df235SSean Wang }
5388174a851SLight Hsieh EXPORT_SYMBOL_GPL(mtk_eint_do_init);
5398174a851SLight Hsieh
5408174a851SLight Hsieh MODULE_LICENSE("GPL v2");
5418174a851SLight Hsieh MODULE_DESCRIPTION("MediaTek EINT Driver");
542