xref: /linux/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml (revision a110f942672c8995dc1cacb5a44c6730856743aa)
1*d8d357b8SIgor Belwon# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*d8d357b8SIgor Belwon%YAML 1.2
3*d8d357b8SIgor Belwon---
4*d8d357b8SIgor Belwon$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6878-pinctrl.yaml#
5*d8d357b8SIgor Belwon$schema: http://devicetree.org/meta-schemas/core.yaml#
6*d8d357b8SIgor Belwon
7*d8d357b8SIgor Belwontitle: MediaTek MT6878 Pin Controller
8*d8d357b8SIgor Belwon
9*d8d357b8SIgor Belwonmaintainers:
10*d8d357b8SIgor Belwon  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11*d8d357b8SIgor Belwon  - Igor Belwon <igor.belwon@mentallysanemainliners.org>
12*d8d357b8SIgor Belwon
13*d8d357b8SIgor Belwondescription:
14*d8d357b8SIgor Belwon  The MediaTek MT6878 Pin controller is used to control SoC pins.
15*d8d357b8SIgor Belwon
16*d8d357b8SIgor Belwonproperties:
17*d8d357b8SIgor Belwon  compatible:
18*d8d357b8SIgor Belwon    const: mediatek,mt6878-pinctrl
19*d8d357b8SIgor Belwon
20*d8d357b8SIgor Belwon  reg:
21*d8d357b8SIgor Belwon    items:
22*d8d357b8SIgor Belwon      - description: pin controller base
23*d8d357b8SIgor Belwon      - description: bl group IO
24*d8d357b8SIgor Belwon      - description: bm group IO
25*d8d357b8SIgor Belwon      - description: br group IO
26*d8d357b8SIgor Belwon      - description: bl1 group IO
27*d8d357b8SIgor Belwon      - description: br1 group IO
28*d8d357b8SIgor Belwon      - description: lm group IO
29*d8d357b8SIgor Belwon      - description: lt group IO
30*d8d357b8SIgor Belwon      - description: rm group IO
31*d8d357b8SIgor Belwon      - description: rt group IO
32*d8d357b8SIgor Belwon      - description: EINT controller E block
33*d8d357b8SIgor Belwon      - description: EINT controller S block
34*d8d357b8SIgor Belwon      - description: EINT controller W block
35*d8d357b8SIgor Belwon      - description: EINT controller C block
36*d8d357b8SIgor Belwon
37*d8d357b8SIgor Belwon  reg-names:
38*d8d357b8SIgor Belwon    items:
39*d8d357b8SIgor Belwon      - const: base
40*d8d357b8SIgor Belwon      - const: bl
41*d8d357b8SIgor Belwon      - const: bm
42*d8d357b8SIgor Belwon      - const: br
43*d8d357b8SIgor Belwon      - const: bl1
44*d8d357b8SIgor Belwon      - const: br1
45*d8d357b8SIgor Belwon      - const: lm
46*d8d357b8SIgor Belwon      - const: lt
47*d8d357b8SIgor Belwon      - const: rm
48*d8d357b8SIgor Belwon      - const: rt
49*d8d357b8SIgor Belwon      - const: eint-e
50*d8d357b8SIgor Belwon      - const: eint-s
51*d8d357b8SIgor Belwon      - const: eint-w
52*d8d357b8SIgor Belwon      - const: eint-c
53*d8d357b8SIgor Belwon
54*d8d357b8SIgor Belwon  gpio-controller: true
55*d8d357b8SIgor Belwon
56*d8d357b8SIgor Belwon  '#gpio-cells':
57*d8d357b8SIgor Belwon    description:
58*d8d357b8SIgor Belwon      Number of cells in GPIO specifier. Since the generic GPIO binding is used,
59*d8d357b8SIgor Belwon      the amount of cells must be specified as 2. See the below mentioned gpio
60*d8d357b8SIgor Belwon      binding representation for description of particular cells.
61*d8d357b8SIgor Belwon    const: 2
62*d8d357b8SIgor Belwon
63*d8d357b8SIgor Belwon  gpio-ranges:
64*d8d357b8SIgor Belwon    maxItems: 1
65*d8d357b8SIgor Belwon
66*d8d357b8SIgor Belwon  gpio-line-names:
67*d8d357b8SIgor Belwon    maxItems: 216
68*d8d357b8SIgor Belwon
69*d8d357b8SIgor Belwon  interrupts:
70*d8d357b8SIgor Belwon    description: The interrupt outputs to sysirq
71*d8d357b8SIgor Belwon    maxItems: 1
72*d8d357b8SIgor Belwon
73*d8d357b8SIgor Belwon  interrupt-controller: true
74*d8d357b8SIgor Belwon
75*d8d357b8SIgor Belwon  '#interrupt-cells':
76*d8d357b8SIgor Belwon    const: 2
77*d8d357b8SIgor Belwon
78*d8d357b8SIgor Belwon# PIN CONFIGURATION NODES
79*d8d357b8SIgor BelwonpatternProperties:
80*d8d357b8SIgor Belwon  '-pins$':
81*d8d357b8SIgor Belwon    type: object
82*d8d357b8SIgor Belwon    additionalProperties: false
83*d8d357b8SIgor Belwon
84*d8d357b8SIgor Belwon    patternProperties:
85*d8d357b8SIgor Belwon      '^pins':
86*d8d357b8SIgor Belwon        type: object
87*d8d357b8SIgor Belwon        allOf:
88*d8d357b8SIgor Belwon          - $ref: /schemas/pinctrl/pincfg-node.yaml
89*d8d357b8SIgor Belwon          - $ref: /schemas/pinctrl/pinmux-node.yaml
90*d8d357b8SIgor Belwon        description:
91*d8d357b8SIgor Belwon          A pinctrl node should contain at least one subnodes representing the
92*d8d357b8SIgor Belwon          pinctrl groups available on the machine. Each subnode will list the
93*d8d357b8SIgor Belwon          pins it needs, and how they should be configured, with regard to muxer
94*d8d357b8SIgor Belwon          configuration, pullups, drive strength, input enable/disable and input
95*d8d357b8SIgor Belwon          schmitt.
96*d8d357b8SIgor Belwon
97*d8d357b8SIgor Belwon        properties:
98*d8d357b8SIgor Belwon          pinmux:
99*d8d357b8SIgor Belwon            description:
100*d8d357b8SIgor Belwon              Integer array, represents gpio pin number and mux setting.
101*d8d357b8SIgor Belwon              Supported pin number and mux are defined as macros in
102*d8d357b8SIgor Belwon              arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h for this SoC.
103*d8d357b8SIgor Belwon
104*d8d357b8SIgor Belwon          drive-strength:
105*d8d357b8SIgor Belwon            enum: [2, 4, 6, 8, 10, 12, 14, 16]
106*d8d357b8SIgor Belwon
107*d8d357b8SIgor Belwon          drive-strength-microamp:
108*d8d357b8SIgor Belwon            enum: [125, 250, 500, 1000]
109*d8d357b8SIgor Belwon
110*d8d357b8SIgor Belwon          bias-pull-down:
111*d8d357b8SIgor Belwon            oneOf:
112*d8d357b8SIgor Belwon              - type: boolean
113*d8d357b8SIgor Belwon              - enum: [75000, 5000]
114*d8d357b8SIgor Belwon                description: Pull down RSEL type resistance values (in ohms)
115*d8d357b8SIgor Belwon            description:
116*d8d357b8SIgor Belwon              For normal pull down type there is no need to specify a resistance
117*d8d357b8SIgor Belwon              value, hence this can be specified as a boolean property.
118*d8d357b8SIgor Belwon              For RSEL pull down type a resistance value (in ohms) can be added.
119*d8d357b8SIgor Belwon
120*d8d357b8SIgor Belwon          bias-pull-up:
121*d8d357b8SIgor Belwon            oneOf:
122*d8d357b8SIgor Belwon              - type: boolean
123*d8d357b8SIgor Belwon              - enum: [10000, 5000, 4000, 3000]
124*d8d357b8SIgor Belwon                description: Pull up RSEL type resistance values (in ohms)
125*d8d357b8SIgor Belwon            description:
126*d8d357b8SIgor Belwon              For normal pull up type there is no need to specify a resistance
127*d8d357b8SIgor Belwon              value, hence this can be specified as a boolean property.
128*d8d357b8SIgor Belwon              For RSEL pull up type a resistance value (in ohms) can be added.
129*d8d357b8SIgor Belwon
130*d8d357b8SIgor Belwon          bias-disable: true
131*d8d357b8SIgor Belwon
132*d8d357b8SIgor Belwon          output-high: true
133*d8d357b8SIgor Belwon
134*d8d357b8SIgor Belwon          output-low: true
135*d8d357b8SIgor Belwon
136*d8d357b8SIgor Belwon          input-enable: true
137*d8d357b8SIgor Belwon
138*d8d357b8SIgor Belwon          input-disable: true
139*d8d357b8SIgor Belwon
140*d8d357b8SIgor Belwon          input-schmitt-enable: true
141*d8d357b8SIgor Belwon
142*d8d357b8SIgor Belwon          input-schmitt-disable: true
143*d8d357b8SIgor Belwon
144*d8d357b8SIgor Belwon        required:
145*d8d357b8SIgor Belwon          - pinmux
146*d8d357b8SIgor Belwon
147*d8d357b8SIgor Belwon        additionalProperties: false
148*d8d357b8SIgor Belwon
149*d8d357b8SIgor Belwonrequired:
150*d8d357b8SIgor Belwon  - compatible
151*d8d357b8SIgor Belwon  - reg
152*d8d357b8SIgor Belwon  - interrupts
153*d8d357b8SIgor Belwon  - interrupt-controller
154*d8d357b8SIgor Belwon  - '#interrupt-cells'
155*d8d357b8SIgor Belwon  - gpio-controller
156*d8d357b8SIgor Belwon  - '#gpio-cells'
157*d8d357b8SIgor Belwon  - gpio-ranges
158*d8d357b8SIgor Belwon
159*d8d357b8SIgor BelwonadditionalProperties: false
160*d8d357b8SIgor Belwon
161*d8d357b8SIgor Belwonexamples:
162*d8d357b8SIgor Belwon  - |
163*d8d357b8SIgor Belwon    #include <dt-bindings/interrupt-controller/arm-gic.h>
164*d8d357b8SIgor Belwon    #include <dt-bindings/pinctrl/mt65xx.h>
165*d8d357b8SIgor Belwon    #define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
166*d8d357b8SIgor Belwon    #define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1)
167*d8d357b8SIgor Belwon    #define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1)
168*d8d357b8SIgor Belwon
169*d8d357b8SIgor Belwon    pio: pinctrl@10005000 {
170*d8d357b8SIgor Belwon        compatible = "mediatek,mt6878-pinctrl";
171*d8d357b8SIgor Belwon        reg = <0x10005000 0x1000>,
172*d8d357b8SIgor Belwon              <0x11d10000 0x1000>,
173*d8d357b8SIgor Belwon              <0x11d30000 0x1000>,
174*d8d357b8SIgor Belwon              <0x11d40000 0x1000>,
175*d8d357b8SIgor Belwon              <0x11d50000 0x1000>,
176*d8d357b8SIgor Belwon              <0x11d60000 0x1000>,
177*d8d357b8SIgor Belwon              <0x11e20000 0x1000>,
178*d8d357b8SIgor Belwon              <0x11e30000 0x1000>,
179*d8d357b8SIgor Belwon              <0x11eb0000 0x1000>,
180*d8d357b8SIgor Belwon              <0x11ec0000 0x1000>,
181*d8d357b8SIgor Belwon              <0x11ce0000 0x1000>,
182*d8d357b8SIgor Belwon              <0x11de0000 0x1000>,
183*d8d357b8SIgor Belwon              <0x11e60000 0x1000>,
184*d8d357b8SIgor Belwon              <0x1c01e000 0x1000>;
185*d8d357b8SIgor Belwon        reg-names = "base", "bl", "bm", "br", "bl1", "br1",
186*d8d357b8SIgor Belwon                    "lm", "lt", "rm", "rt", "eint-e", "eint-s",
187*d8d357b8SIgor Belwon                    "eint-w", "eint-c";
188*d8d357b8SIgor Belwon        gpio-controller;
189*d8d357b8SIgor Belwon        #gpio-cells = <2>;
190*d8d357b8SIgor Belwon        gpio-ranges = <&pio 0 0 220>;
191*d8d357b8SIgor Belwon        interrupt-controller;
192*d8d357b8SIgor Belwon        interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
193*d8d357b8SIgor Belwon        #interrupt-cells = <2>;
194*d8d357b8SIgor Belwon
195*d8d357b8SIgor Belwon        gpio-pins {
196*d8d357b8SIgor Belwon            pins {
197*d8d357b8SIgor Belwon                pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
198*d8d357b8SIgor Belwon                bias-pull-up = <4000>;
199*d8d357b8SIgor Belwon                drive-strength = <6>;
200*d8d357b8SIgor Belwon            };
201*d8d357b8SIgor Belwon        };
202*d8d357b8SIgor Belwon
203*d8d357b8SIgor Belwon        i2c0-pins {
204*d8d357b8SIgor Belwon            pins-bus {
205*d8d357b8SIgor Belwon                pinmux = <PINMUX_GPIO99__FUNC_SCL0>,
206*d8d357b8SIgor Belwon                         <PINMUX_GPIO100__FUNC_SDA0>;
207*d8d357b8SIgor Belwon                bias-pull-down = <75000>;
208*d8d357b8SIgor Belwon                drive-strength-microamp = <1000>;
209*d8d357b8SIgor Belwon            };
210*d8d357b8SIgor Belwon        };
211*d8d357b8SIgor Belwon    };
212