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/linux/drivers/dma/
H A Dfsl-edma-trace.h16 TP_PROTO(struct fsl_edma_engine *edma, void __iomem *addr, u32 value),
17 TP_ARGS(edma, addr, value),
19 __field(struct fsl_edma_engine *, edma)
25 __entry->edma = edma;
28 __entry->membase = edma->membase;
35 TP_PROTO(struct fsl_edma_engine *edma, void __iomem *addr, u32 value),
36 TP_ARGS(edma, addr, value)
40 TP_PROTO(struct fsl_edma_engine *edma, void __iomem *addr, u32 value),
41 TP_ARGS(edma, addr, value)
45 TP_PROTO(struct fsl_edma_engine *edma, void __iomem *addr, u32 value),
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H A Dfsl-edma-common.h167 struct fsl_edma_engine *edma; member
274 return fsl_chan->edma->drvdata->flags; in fsl_edma_drvflags()
279 __iomem __le64 : edma_readq(chan->edma, &(_tcd)->__name), \
280 __iomem __le32 : edma_readl(chan->edma, &(_tcd)->__name), \
281 __iomem __le16 : edma_readw(chan->edma, &(_tcd)->__name) \
292 __iomem __le64 : edma_writeq(chan->edma, (u64 __force)(_val), &_tcd->__name), \
293 __iomem __le32 : edma_writel(chan->edma, (u32 __force)(_val), &_tcd->__name), \
294 __iomem __le16 : edma_writew(chan->edma, (u16 __force)(_val), &_tcd->__name), \
295 __iomem u8 : edma_writeb(chan->edma, _val, &_tcd->__name) \
323 edma_readl(chan->edma, \
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H A Dfsl-edma-main.c3 * drivers/dma/fsl-edma.c
8 * Driver for the Freescale eDMA engine with flexible channel multiplexing
9 * capability for DMA request sources. The eDMA block can be found on some
13 #include <dt-bindings/dma/fsl-edma.h>
25 #include "fsl-edma-common.h"
150 return fsl_edma_tx_handler(irq, fsl_chan->edma); in fsl_edma2_tx_handler()
349 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); in fsl_edma_irq_init()
353 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); in fsl_edma_irq_init()
359 fsl_edma_irq_handler, 0, "eDMA", fsl_edma); in fsl_edma_irq_init()
361 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); in fsl_edma_irq_init()
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H A Dep93xx_dma.c165 * @edma: pointer to the engine device
194 const struct ep93xx_dma_engine *edma; member
800 edmac->edma->hw_submit(edmac); in ep93xx_dma_advance_work()
858 switch (edmac->edma->hw_interrupt(edmac)) { in ep93xx_dma_interrupt()
906 edmac->edma->hw_submit(edmac); in ep93xx_dma_tx_submit()
930 if (!edmac->edma->m2m) { in ep93xx_dma_alloc_chan_resources()
959 ret = edmac->edma->hw_setup(edmac); in ep93xx_dma_alloc_chan_resources()
1011 edmac->edma->hw_shutdown(edmac); in ep93xx_dma_free_chan_resources()
1093 if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) { in ep93xx_dma_prep_slave_sg()
1174 if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) { in ep93xx_dma_prep_dma_cyclic()
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/linux/Documentation/devicetree/bindings/dma/
H A Dti-edma.txt1 Texas Instruments eDMA
20 - reg: Memory map of eDMA CC
24 - ti,tptcs: List of TPTCs associated with the eDMA in the following form:
30 - ti,hwmods: Name of the hwmods associated to the eDMA CC.
40 - ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
42 - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
46 Single uint32 for EDMA with 32 channels, array of two uint32 for
47 EDMA with 64 channels. See example and
61 - reg: Memory map of eDMA TC
67 - ti,hwmods: Name of the hwmods associated to the eDMA TC.
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H A Dti-dma-crossbar.txt5 "ti,am335x-edma-crossbar" for AM335x and AM437x
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
20 memcpy channels in eDMA.
26 For ti,am335x-edma-crossbar: the meaning of parameters of dmas for clients:
29 When mux 0 is used the DMA channel can be requested directly from edma node.
/linux/drivers/dma/dw-edma/
H A DMakefile3 obj-$(CONFIG_DW_EDMA) += dw-edma.o
4 dw-edma-$(CONFIG_DEBUG_FS) := dw-edma-v0-debugfs.o \
6 dw-edma-objs := dw-edma-core.o \
7 dw-edma-v0-core.o \
8 dw-hdma-v0-core.o $(dw-edma-y)
9 obj-$(CONFIG_DW_EDMA_PCIE) += dw-edma-pcie.o
H A DKconfig4 tristate "Synopsys DesignWare eDMA controller driver"
9 Support the Synopsys DesignWare eDMA controller, normally
15 tristate "Synopsys DesignWare eDMA PCIe driver"
19 eDMA controller and an endpoint PCIe device. This also serves
H A Ddw-edma-v0-debugfs.c4 * Synopsys DesignWare eDMA v0 core
12 #include "dw-edma-v0-debugfs.h"
13 #include "dw-edma-v0-regs.h"
14 #include "dw-edma-core.h"
143 /* eDMA global registers */ in dw_edma_debugfs_regs_wr()
148 /* eDMA interrupts registers */ in dw_edma_debugfs_regs_wr()
164 /* eDMA channel context grouping */ in dw_edma_debugfs_regs_wr()
205 /* eDMA global registers */ in dw_edma_debugfs_regs_rd()
210 /* eDMA interrupts registers */ in dw_edma_debugfs_regs_rd()
227 /* eDMA channel context grouping */ in dw_edma_debugfs_regs_rd()
H A Ddw-edma-pcie.c4 * Synopsys DesignWare eDMA PCIe driver
13 #include <linux/dma/edma.h>
19 #include "dw-edma-core.h"
64 /* eDMA registers location */
66 /* eDMA memory linked list location */
69 /* eDMA memory data location */
98 /* eDMA registers location */
102 /* eDMA memory linked list location */
115 /* eDMA memory data location */
444 pci_err(pdev, "eDMA BAR I/O remapping failed\n"); in dw_edma_pcie_probe()
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H A Ddw-edma-v0-core.h4 * Synopsys DesignWare eDMA v0 core
12 #include <linux/dma/edma.h>
14 /* eDMA core register */
H A Ddw-edma-v0-debugfs.h4 * Synopsys DesignWare eDMA v0 core
12 #include <linux/dma/edma.h>
H A Ddw-edma-v0-core.c4 * Synopsys DesignWare eDMA v0 core
14 #include "dw-edma-core.h"
15 #include "dw-edma-v0-core.h"
16 #include "dw-edma-v0-regs.h"
17 #include "dw-edma-v0-debugfs.h"
170 /* eDMA management callbacks */
278 * The unrolled eDMA and HDMA compatibility register maps share interrupt
486 * In case of remote eDMA engine setup, the DW PCIe RP/EP internal in dw_edma_v0_sync_ll_data()
619 /* eDMA debugfs callbacks */
H A Ddw-edma-v0-regs.h4 * Synopsys DesignWare eDMA v0 core
108 /* eDMA global registers */
134 /* eDMA interrupts registers */
195 /* eDMA channel context grouping */
/linux/include/linux/dma/
H A Dedma.h4 * Synopsys DesignWare eDMA core driver
32 * struct dw_edma_plat_ops - platform-specific eDMA methods
33 * @irq_vector: Get IRQ number of the passed eDMA channel. Note the
35 * numbering with the eDMA write channels being placed
40 * the DW PCIe RP/EP controller with the DW eDMA device in
58 * enum dw_edma_chip_flags - Flags specific to an eDMA chip
59 * @DW_EDMA_CHIP_LOCAL: eDMA is used locally by an endpoint
78 * DesignWare EP eDMA can signal interrupts locally through the edma_int[]
82 * For the v0 eDMA linked-list programming path, DMA_*_INT_MASK gates the local
105 * struct dw_edma_chip - representation of DesignWare eDMA controller hardware
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/linux/sound/soc/ti/
H A Dedma-pcm.c3 * edma-pcm.c - eDMA PCM driver using dmaengine for AM3xxx, AM4xxx
19 #include "edma-pcm.h"
31 .periods_max = 19, /* Limit by edma dmaengine driver */
62 MODULE_DESCRIPTION("eDMA PCM ASoC platform driver");
H A DMakefile4 snd-soc-ti-edma-y := edma-pcm.o
8 obj-$(CONFIG_SND_SOC_TI_EDMA_PCM) += snd-soc-ti-edma.o
H A Dedma-pcm.h3 * edma-pcm.h - eDMA PCM driver using dmaengine for AM3xxx, AM4xxx
/linux/Documentation/devicetree/bindings/pci/
H A Dsnps,dw-pcie-ep.yaml47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
68 iATU/eDMA registers common for all device functions. It's an
74 normally mapped to the 0x0 address of this region, while eDMA
78 Platform-specific eDMA registers. Some platforms may have eDMA
135 Indicates that the eDMA Tx/Rx transfer is complete or that an
136 error has occurred on the corresponding channel. eDMA can have
137 eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
138 to 16 IRQ signals all together. Write eDMA channels shall go
H A Dsnps,dw-pcie.yaml56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
77 iATU/eDMA registers common for all device functions. It's an
83 normally mapped to the 0x0 address of this region, while eDMA
87 Platform-specific eDMA registers. Some platforms may have eDMA
148 Indicates that the eDMA Tx/Rx transfer is complete or that an
149 error has occurred on the corresponding channel. eDMA can have
150 eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
151 to 16 IRQ signals all together. Write eDMA channels shall go
H A Drockchip-dw-pcie-common.yaml71 If the matching interrupt name is "dma0", then this is the eDMA write
74 eDMA write channel 1 interrupt
76 eDMA read channel 0 interrupt
78 eDMA read channel 1 interrupt
/linux/include/linux/platform_data/
H A Dedma.h3 * TI EDMA definitions
22 * buffer or for several discontiguous smaller buffers. An EDMA transfer
28 * The EDMA Channel Controller (CC) maps requests from channels into physical
62 /* platform_data for EDMA driver */
/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850-enbw-cmc.dts39 ti,edma-reserved-slot-ranges = <32 50>;
43 ti,edma-reserved-slot-ranges = <32 90>;
/linux/drivers/dma/ti/
H A Dedma.c3 * TI EDMA DMA engine driver
26 #include <linux/platform_data/edma.h>
43 /* Offsets for EDMA CC global channel registers and their shadows */
67 /* Offsets for EDMA CC global registers */
187 * refers to the number of pending transfer (programmed to EDMA
509 dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n"); in edma_link()
554 /* EDMA channels without event association */ in edma_start()
559 /* EDMA channel with event association */ in edma_start()
597 * Temporarily disable EDMA hardware events on the specified channel,
609 /* Re-enable EDMA hardware events on the specified channel. */
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/linux/Documentation/devicetree/bindings/mfd/
H A Dti,am3359-tscadc.yaml77 dmas = <&edma 53 0>, <&edma 57 0>;

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