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/linux/Documentation/devicetree/bindings/dma/
H A Dfsl,edma.yaml4 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
7 title: Freescale enhanced Direct Memory Access(eDMA) Controller
10 The eDMA channels have multiplex capability by programmable
22 - fsl,vf610-edma
23 - fsl,imx7ulp-edma
24 - fsl,imx8qm-edma
25 - fsl,imx8ulp-edma
29 - nxp,s32g2-edma
39 - const: fsl,ls1028a-edma
40 - const: fsl,vf610-edma
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H A Dti-edma.txt1 Texas Instruments eDMA
20 - reg: Memory map of eDMA CC
24 - ti,tptcs: List of TPTCs associated with the eDMA in the following form:
30 - ti,hwmods: Name of the hwmods associated to the eDMA CC.
40 - ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
42 - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
46 Single uint32 for EDMA with 32 channels, array of two uint32 for
47 EDMA with 64 channels. See example and
61 - reg: Memory map of eDMA TC
67 - ti,hwmods: Name of the hwmods associated to the eDMA TC.
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H A Dti-dma-crossbar.txt5 "ti,am335x-edma-crossbar" for AM335x and AM437x
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
20 memcpy channels in eDMA.
26 For ti,am335x-edma-crossbar: the meaning of parameters of dmas for clients:
29 When mux 0 is used the DMA channel can be requested directly from edma node.
/linux/drivers/dma/
H A Dfsl-edma-common.c15 #include "fsl-edma-common.h"
93 if (!edma_readl(fsl_chan->edma, fsl_chan->mux_addr)) in fsl_edma3_enable_request()
94 edma_writel(fsl_chan->edma, fsl_chan->srcid, fsl_chan->mux_addr); in fsl_edma3_enable_request()
104 struct edma_regs *regs = &fsl_chan->edma->regs; in fsl_edma_enable_request()
110 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { in fsl_edma_enable_request()
111 edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); in fsl_edma_enable_request()
112 edma_writeb(fsl_chan->edma, ch, regs->serq); in fsl_edma_enable_request()
130 edma_writel(fsl_chan->edma, 0, fsl_chan->mux_addr); in fsl_edma3_disable_request()
138 struct edma_regs *regs = &fsl_chan->edma->regs; in fsl_edma_disable_request()
144 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { in fsl_edma_disable_request()
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H A Dfsl-edma-common.h167 struct fsl_edma_engine *edma; member
274 return fsl_chan->edma->drvdata->flags; in fsl_edma_drvflags()
279 __iomem __le64 : edma_readq(chan->edma, &(_tcd)->__name), \
280 __iomem __le32 : edma_readl(chan->edma, &(_tcd)->__name), \
281 __iomem __le16 : edma_readw(chan->edma, &(_tcd)->__name) \
292 __iomem __le64 : edma_writeq(chan->edma, (u64 __force)(_val), &_tcd->__name), \
293 __iomem __le32 : edma_writel(chan->edma, (u32 __force)(_val), &_tcd->__name), \
294 __iomem __le16 : edma_writew(chan->edma, (u16 __force)(_val), &_tcd->__name), \
295 __iomem u8 : edma_writeb(chan->edma, _val, &_tcd->__name) \
323 edma_readl(chan->edma, \
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H A DMakefile32 obj-$(CONFIG_DW_EDMA) += dw-edma/
34 fsl-edma-trace-$(CONFIG_TRACING) := fsl-edma-trace.o
35 CFLAGS_fsl-edma-trace.o := -I$(src)
37 fsl-edma-objs := fsl-edma-main.o fsl-edma-common.o ${fsl-edma-trace-y}
38 obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
39 mcf-edma-objs := mcf-edma-main.o fsl-edma-common.o ${fsl-edma-trace-y}
40 obj-$(CONFIG_MCF_EDMA) += mcf-edma.o
H A Dep93xx_dma.c166 * @edma: pointer to the engine device
195 const struct ep93xx_dma_engine *edma; member
801 edmac->edma->hw_submit(edmac); in ep93xx_dma_advance_work()
859 switch (edmac->edma->hw_interrupt(edmac)) { in ep93xx_dma_interrupt()
907 edmac->edma->hw_submit(edmac); in ep93xx_dma_tx_submit()
931 if (!edmac->edma->m2m) { in ep93xx_dma_alloc_chan_resources()
960 ret = edmac->edma->hw_setup(edmac); in ep93xx_dma_alloc_chan_resources()
1012 edmac->edma->hw_shutdown(edmac); in ep93xx_dma_free_chan_resources()
1094 if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) { in ep93xx_dma_prep_slave_sg()
1175 if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) { in ep93xx_dma_prep_dma_cyclic()
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/linux/drivers/dma/dw-edma/
H A DMakefile3 obj-$(CONFIG_DW_EDMA) += dw-edma.o
4 dw-edma-$(CONFIG_DEBUG_FS) := dw-edma-v0-debugfs.o \
6 dw-edma-objs := dw-edma-core.o \
7 dw-edma-v0-core.o \
8 dw-hdma-v0-core.o $(dw-edma-y)
9 obj-$(CONFIG_DW_EDMA_PCIE) += dw-edma-pcie.o
H A Ddw-edma-pcie.c4 * Synopsys DesignWare eDMA PCIe driver
13 #include <linux/dma/edma.h>
18 #include "dw-edma-core.h"
40 /* eDMA registers location */
42 /* eDMA memory linked list location */
45 /* eDMA memory data location */
56 /* eDMA registers location */
60 /* eDMA memory linked list location */
73 /* eDMA memory data location */
201 pci_err(pdev, "eDMA BAR I/O remapping failed\n"); in dw_edma_pcie_probe()
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H A DKconfig4 tristate "Synopsys DesignWare eDMA controller driver"
9 Support the Synopsys DesignWare eDMA controller, normally
15 tristate "Synopsys DesignWare eDMA PCIe driver"
19 eDMA controller and an endpoint PCIe device. This also serves
H A Ddw-edma-v0-debugfs.c4 * Synopsys DesignWare eDMA v0 core
12 #include "dw-edma-v0-debugfs.h"
13 #include "dw-edma-v0-regs.h"
14 #include "dw-edma-core.h"
143 /* eDMA global registers */ in dw_edma_debugfs_regs_wr()
148 /* eDMA interrupts registers */ in dw_edma_debugfs_regs_wr()
164 /* eDMA channel context grouping */ in dw_edma_debugfs_regs_wr()
205 /* eDMA global registers */ in dw_edma_debugfs_regs_rd()
210 /* eDMA interrupts registers */ in dw_edma_debugfs_regs_rd()
227 /* eDMA channel context grouping */ in dw_edma_debugfs_regs_rd()
H A Ddw-edma-v0-core.h4 * Synopsys DesignWare eDMA v0 core
12 #include <linux/dma/edma.h>
14 /* eDMA core register */
H A Ddw-edma-v0-core.c4 * Synopsys DesignWare eDMA v0 core
13 #include "dw-edma-core.h"
14 #include "dw-edma-v0-core.h"
15 #include "dw-edma-v0-regs.h"
16 #include "dw-edma-v0-debugfs.h"
162 /* eDMA management callbacks */
352 * In case of remote eDMA engine setup, the DW PCIe RP/EP internal in dw_edma_v0_sync_ll_data()
506 /* eDMA debugfs callbacks */
H A Ddw-edma-core.c4 * Synopsys DesignWare eDMA core driver
16 #include <linux/dma/edma.h>
20 #include "dw-edma-core.h"
21 #include "dw-edma-v0-core.h"
78 * inform the eDMA HW block that this is a new linked list ready in dw_edma_alloc_chunk()
378 * If eDMA is embedded into the DW PCIe RP/EP and controlled from the in dw_edma_device_transfer()
384 * If eDMA is embedded into a Remote PCIe EP and is controlled by the in dw_edma_device_transfer()
965 snprintf(dw->name, sizeof(dw->name), "dw-edma-core:%s", in dw_edma_probe()
968 /* Disable eDMA, only to establish the ideal initial conditions */ in dw_edma_probe()
1007 /* Disable eDMA */ in dw_edma_remove()
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H A Ddw-edma-v0-debugfs.h4 * Synopsys DesignWare eDMA v0 core
12 #include <linux/dma/edma.h>
/linux/Documentation/devicetree/bindings/pci/
H A Dsnps,dw-pcie-ep.yaml47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
68 iATU/eDMA registers common for all device functions. It's an
74 normally mapped to the 0x0 address of this region, while eDMA
78 Platform-specific eDMA registers. Some platforms may have eDMA
135 Indicates that the eDMA Tx/Rx transfer is complete or that an
136 error has occurred on the corresponding channel. eDMA can have
137 eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
138 to 16 IRQ signals all together. Write eDMA channels shall go
H A Dsnps,dw-pcie.yaml56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
77 iATU/eDMA registers common for all device functions. It's an
83 normally mapped to the 0x0 address of this region, while eDMA
87 Platform-specific eDMA registers. Some platforms may have eDMA
148 Indicates that the eDMA Tx/Rx transfer is complete or that an
149 error has occurred on the corresponding channel. eDMA can have
150 eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
151 to 16 IRQ signals all together. Write eDMA channels shall go
H A Drockchip-dw-pcie-common.yaml71 If the matching interrupt name is "dma0", then this is the eDMA write
74 eDMA write channel 1 interrupt
76 eDMA read channel 0 interrupt
78 eDMA read channel 1 interrupt
/linux/sound/soc/ti/
H A Dedma-pcm.c3 * edma-pcm.c - eDMA PCM driver using dmaengine for AM3xxx, AM4xxx
19 #include "edma-pcm.h"
31 .periods_max = 19, /* Limit by edma dmaengine driver */
62 MODULE_DESCRIPTION("eDMA PCM ASoC platform driver");
H A DMakefile4 snd-soc-ti-edma-y := edma-pcm.o
8 obj-$(CONFIG_SND_SOC_TI_EDMA_PCM) += snd-soc-ti-edma.o
H A Dedma-pcm.h3 * edma-pcm.h - eDMA PCM driver using dmaengine for AM3xxx, AM4xxx
/linux/include/linux/platform_data/
H A Ddma-mcf-edma.h3 * Freescale eDMA platform data, ColdFire SoC's family.
27 * struct mcf_edma_platform_data - platform specific data for eDMA engine
29 * @ver The eDMA module version.
30 * @dma_channels The number of eDMA channels.
H A Dedma.h3 * TI EDMA definitions
22 * buffer or for several discontiguous smaller buffers. An EDMA transfer
28 * The EDMA Channel Controller (CC) maps requests from channels into physical
62 /* platform_data for EDMA driver */
/linux/drivers/dma/ti/
H A Dedma.c3 * TI EDMA DMA engine driver
26 #include <linux/platform_data/edma.h>
43 /* Offsets for EDMA CC global channel registers and their shadows */
67 /* Offsets for EDMA CC global registers */
187 * refers to the number of pending transfer (programmed to EDMA
509 dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n"); in edma_link()
554 /* EDMA channels without event association */ in edma_start()
559 /* EDMA channel with event association */ in edma_start()
597 * Temporarily disable EDMA hardware events on the specified channel,
609 /* Re-enable EDMA hardware events on the specified channel. */
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/linux/drivers/ata/
H A Dsata_mv.c311 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
395 EDMA_CMD = 0x28, /* EDMA command register */
396 EDMA_EN = (1 << 0), /* enable EDMA */
397 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
400 EDMA_STATUS = 0x30, /* EDMA engine status */
402 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
425 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
431 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
432 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
433 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
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