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/linux/drivers/irqchip/
H A Dqcom-pdc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
47 #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base)
79 /* Use previous DRV (client) region and shift to bank 3-4 */ in pdc_x1e_irq_enable_write()
84 /* Use our own region and shift to bank 0-2 */ in pdc_x1e_irq_enable_write()
86 bank -= 2; in pdc_x1e_irq_enable_write()
129 __pdc_enable_intr(d->hwirq, on); in pdc_enable_intr()
146 * GIC does not handle falling edge or active low. To allow falling edge and
148 * falling edge into a rising edge and active low into an active high.
151 * Level sensitive active low LOW
[all …]
H A Dirq-mst-intc.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
4 * Author Mark-PK Tsai <mark-pk.tsai@mediatek.com>
49 raw_spin_lock_irqsave(&cd->lock, flags); in mst_set_irq()
50 val = readw_relaxed(cd->base + offset) | mask; in mst_set_irq()
51 writew_relaxed(val, cd->base + offset); in mst_set_irq()
52 raw_spin_unlock_irqrestore(&cd->lock, flags); in mst_set_irq()
65 raw_spin_lock_irqsave(&cd->lock, flags); in mst_clear_irq()
66 val = readw_relaxed(cd->base + offset) & ~mask; in mst_clear_irq()
67 writew_relaxed(val, cd->base + offset); in mst_clear_irq()
68 raw_spin_unlock_irqrestore(&cd->lock, flags); in mst_clear_irq()
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dimg,pdc-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/img,pdc-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - James Hogan <jhogan@kernel.org>
19 const: img,pdc-intc
24 interrupt-controller: true
26 '#interrupt-cells':
28 <1st-cell>: The interrupt-number that identifies the interrupt source.
29 0-7: Peripheral interrupts
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H A Darm,gic-v5-iwb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5-iwb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lpieralisi@kernel.org>
11 - Marc Zyngier <maz@kernel.org>
24 - $ref: /schemas/interrupt-controller.yaml#
28 const: arm,gic-v5-iwb
32 - description: IWB control frame
34 "#address-cells":
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H A Dinterrupts.txt5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
25 The "interrupts-extended" property is a special form; useful when a node needs
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
34 -----------------------------
36 A device is marked as an interrupt controller with the "interrupt-controller"
37 property. This is a empty, boolean property. An additional "#interrupt-cells"
45 -----------
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H A Darm,gic-v5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lpieralisi@kernel.org>
11 - Marc Zyngier <maz@kernel.org>
21 - one or more IRS (Interrupt Routing Service)
22 - zero or more ITS (Interrupt Translation Service)
25 - PE-Private Peripheral Interrupts (PPI)
26 - Shared Peripheral Interrupts (SPI)
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H A Dsnps,archs-idu-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/snps,archs-idu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARC-HS Interrupt Distribution Unit
10 - Vineet Gupta <vgupta@kernel.org>
13 ARC-HS Interrupt Distribution Unit is an optional 2nd level interrupt
22 const: snps,archs-idu-intc
24 interrupt-controller: true
26 '#interrupt-cells':
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H A Dmediatek,mtk-cirq.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mediatek,mtk-cirq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Youlin Pei <youlin.pei@mediatek.com>
14 work outside of MCUSYS which comprises with Cortex-Ax cores, CCI and GIC.
16 to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
25 - enum:
26 - mediatek,mt2701-cirq
27 - mediatek,mt8135-cirq
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H A Dfsl,mpic-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mpic-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Freescale hypervisor and msi-address-64
11 -------------------------------------------
39 this. The address specified in the msi-address-64 property is the PCI
44 - J. Neuschäfer <j.ne@posteo.net>
49 - enum:
50 - fsl,mpic-msi
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/linux/Documentation/devicetree/bindings/gpio/
H A Dnvidia,tegra20-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-gpio
18 - nvidia,tegra30-gpio
[all …]
H A Dsocionext,uniphier-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
27 interrupt-controller: true
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/linux/Documentation/virt/kvm/devices/
H A Dxics.rst1 .. SPDX-License-Identifier: GPL-2.0
25 -EINVAL Value greater than KVM_MAX_VCPU_IDS.
26 -EFAULT Invalid user pointer for attr->addr.
27 -EBUSY A vcpu is already connected to the device.
32 sources, each identified by a 20-bit source number, and a set of
43 least-significant end of the word:
50 * Pending IPI (inter-processor interrupt) priority, 8 bits
64 bitfields, starting from the least-significant end of the word:
77 * Level sensitive flag, 1 bit
79 This bit is 1 for a level-sensitive interrupt source, or 0 for
[all …]
/linux/arch/arm64/kvm/vgic/
H A Dvgic-v2.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/irqchip/arm-gic.h>
31 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2; in vgic_v2_set_underflow()
33 cpuif->vgic_hcr |= GICH_HCR_UIE; in vgic_v2_set_underflow()
44 * - active bit is transferred as is
45 * - pending bit is
46 * - transferred as is in case of edge sensitive IRQs
47 * - set to the line-level (resample time) for level sensitive IRQs
51 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; in vgic_v2_fold_lr_state()
52 struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2; in vgic_v2_fold_lr_state()
[all …]
H A Dvgic.c1 // SPDX-License-Identifier: GPL-2.0-only
26 * kvm->lock (mutex)
27 * vcpu->mutex (mutex)
28 * kvm->arch.config_lock (mutex)
29 * its->cmd_lock (mutex)
30 * its->its_lock (mutex)
31 * vgic_dist->lpi_xa.xa_lock
32 * vgic_cpu->ap_list_lock must be taken with IRQs disabled
33 * vgic_irq->irq_lock must be taken with IRQs disabled
40 * kvm->slots_lock
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/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
158 * 1 Burst R/W Access (Host <-> DPR)
[all …]
/linux/drivers/gpio/
H A Dgpio-rcar.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car GPIO Support
61 #define EDGLEVEL 0x24 /* Edge/level Select Register */
64 #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
71 return ioread32(p->base + offs); in gpio_rcar_read()
77 iowrite32(value, p->base + offs); in gpio_rcar_write()
122 * "Setting Edge-Sensitive Interrupt Input Mode" and in gpio_rcar_config_interrupt_input_mode()
123 * "Setting Level-Sensitive Interrupt Input Mode" in gpio_rcar_config_interrupt_input_mode()
126 raw_spin_lock_irqsave(&p->lock, flags); in gpio_rcar_config_interrupt_input_mode()
131 /* Configure edge or level trigger in EDGLEVEL */ in gpio_rcar_config_interrupt_input_mode()
[all …]
/linux/Documentation/devicetree/bindings/iio/dac/
H A Dadi,ad3530r.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kim Seer Paller <kimseer.paller@analog.com>
13 The AD3530/AD3530R (8-channel) and AD3531/AD3531R (4-channel) are low-power,
14 16-bit, buffered voltage output digital-to-analog converters (DACs) with
15 software-programmable gain controls, providing full-scale output spans of 2.5V
20 https://www.analog.com/media/en/technical-documentation/data-sheets/ad3530_ad530r.pdf
21 https://www.analog.com/media/en/technical-documentation/data-sheets/ad3531-ad3531r.pdf
26 - adi,ad3530
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpc5200.txt2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
[all …]
/linux/drivers/input/mouse/
H A Dbyd.c1 // SPDX-License-Identifier: GPL-2.0-only
38 * Absolute coordinate packets are in the range 0-255 for both X and Y
59 * Swipe gesture from off-pad to on-pad
67 * 1 - 8 : least to most delay
114 * 1 - 7 : least to most sensitive
128 * 2 : edge motion
129 * 3 : free scrolling + edge motion
135 * 1 - 5 : slowest to fastest
139 * Edge motion
146 * Left edge region size
[all …]
/linux/arch/x86/kvm/
H A Di8259.c4 * Copyright (c) 2003-2004 Fabrice Bellard
47 __acquires(&s->lock) in pic_lock()
49 spin_lock(&s->lock); in pic_lock()
53 __releases(&s->lock) in pic_unlock()
55 bool wakeup = s->wakeup_needed; in pic_unlock()
59 s->wakeup_needed = false; in pic_unlock()
61 spin_unlock(&s->lock); in pic_unlock()
64 kvm_for_each_vcpu(i, vcpu, s->kvm) { in pic_unlock()
76 s->isr &= ~(1 << irq); in pic_clear_isr()
77 if (s != &s->pics_state->pics[0]) in pic_clear_isr()
[all …]
/linux/Documentation/arch/arm/
H A Dixp4xx.rst6 -------------------------------------------------------------------------
17 integration such as an on-chip I2C controller.
30 - Dual serial ports
31 - PCI interface
32 - Flash access (MTD/JFFS)
33 - I2C through GPIO on IXP42x
34 - GPIO for input/output/interrupts
35 See arch/arm/mach-ixp4xx/include/mach/platform.h for access functions.
36 - Timers (watchdog, OS)
41 - USB device interface
[all …]
/linux/arch/powerpc/sysdev/xics/
H A Dxics-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
60 ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen); in xics_update_irq_servers()
69 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last in xics_update_irq_servers()
96 index = (1UL << xics_interrupt_server_size) - 1 - gserver; in xics_set_cpu_giq()
100 WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n", in xics_set_cpu_giq()
107 icp_ops->set_priority(LOWEST_PRIORITY); in xics_setup_cpu()
118 xics_ics->mask_unknown(xics_ics, vec); in xics_mask_unknown_vec()
134 BUG_ON(request_irq(ipi, icp_ops->ipi_action, in xics_request_ipi()
144 smp_ops->cause_ipi = icp_ops->cause_ipi; in xics_smp_probe()
157 os_cppr->index = 0; in xics_teardown_cpu()
[all …]
/linux/drivers/mmc/host/
H A Dsdhci-bcm-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/mmc/slot-gpio.h>
16 #include "sdhci-pltfm.h"
63 return -EFAULT; in sdhci_bcm_kona_sd_reset()
72 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) in sdhci_bcm_kona_sd_reset()
73 * Back-to-Back writes to same register needs delay when SD bus clock in sdhci_bcm_kona_sd_reset()
74 * is very low w.r.t AHB clock, mainly during boot-time and during card in sdhci_bcm_kona_sd_reset()
75 * insert-removal. in sdhci_bcm_kona_sd_reset()
97 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) in sdhci_bcm_kona_sd_init()
98 * Back-to-Back writes to same register needs delay when SD bus clock in sdhci_bcm_kona_sd_init()
[all …]
/linux/arch/mips/sibyte/sb1250/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
74 unsigned int irq = d->irq; in sb1250_set_affinity()
114 unsigned int irq = d->irq; in disable_sb1250_irq()
121 unsigned int irq = d->irq; in enable_sb1250_irq()
129 unsigned int irq = d->irq; in ack_sb1250_irq()
162 * Pass 2, the LDT world may be edge-triggered, but in ack_sb1250_irq()
164 * level-sensitive, the EOI is required. in ack_sb1250_irq()
173 .name = "SB1250-IMR",
211 * can do cross-cpu function calls, as required by SMP
244 * inter-cpu messages in arch_init_irq()
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/linux/arch/powerpc/kvm/
H A Dmpic.c63 #define OPENPIC_CPU_REG_SIZE (0x100 + ((MAX_CPU - 1) * 0x1000))
116 struct kvm_vcpu *vcpu = current->thread.kvm_vcpu; in get_current_cpu()
117 return vcpu ? vcpu->arch.irq_cpu_id : -1; in get_current_cpu()
120 return -1; in get_current_cpu()
133 IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
134 IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */
154 bool level:1; /* level-triggered */
171 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
184 /* Count of IRQ sources asserting on non-INT outputs */
248 if (!dst->vcpu) { in mpic_irq_raise()
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