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/linux/drivers/pinctrl/
H A Dpinctrl-xway.c116 MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU),
118 MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU),
126 MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG),
127 MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO),
128 MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU),
129 MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU),
130 MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO),
134 MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO),
135 MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO),
136 MFP_XWAY(GPIO21, GPIO, EBU, MII, EBU2),
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dlantiq,pinctrl-xway.txt55 exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
56 ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
62 spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe
66 exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
67 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
74 spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe
78 exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
79 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
89 spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy
101 spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy
/linux/Documentation/devicetree/bindings/mips/lantiq/
H A Dlantiq,ebu.yaml4 $id: http://devicetree.org/schemas/mips/lantiq/lantiq,ebu.yaml#
7 title: Lantiq Xway SoC series External Bus Unit (EBU)
16 - lantiq,ebu-xway
29 ebu@105300 {
30 compatible = "lantiq,ebu-xway";
/linux/Documentation/sound/cards/
H A Dmixart.rst2 Alsa driver for Digigram miXart8 and miXart8AES/EBU soundcards
13 The miXart8AES/EBU is the same with a add-on card that offers further
16 (AES/EBU, Word Clock, Time Code and Video Synchro)
31 With a miXart8AES/EBU there is in addition 1 stereo digital input
59 digital volume control of each AES/EBU substream.
72 - external clock support (AES/EBU, Word Clock, Time Code, Video Sync)
/linux/drivers/mtd/nand/raw/
H A Dintel-nand-controller.c116 void __iomem *ebu; member
137 return readl_poll_timeout(ctrl->ebu + EBU_WAIT, status, in ebu_nand_waitrdy()
182 writel(0, ebu_host->ebu + EBU_CON); in ebu_nand_disable()
188 void __iomem *nand_con = ebu_host->ebu + EBU_CON; in ebu_select_chip()
231 writel(reg, ctrl->ebu + EBU_BUSCON(ctrl->cs_num)); in ebu_nand_set_timings()
595 ebu_host->ebu = devm_platform_ioremap_resource_byname(pdev, "ebunand"); in ebu_nand_probe()
596 if (IS_ERR(ebu_host->ebu)) in ebu_nand_probe()
597 return PTR_ERR(ebu_host->ebu); in ebu_nand_probe()
669 ebu_host->ebu + EBU_ADDR_SEL(cs)); in ebu_nand_probe()
H A Dxway_nand.c41 /* we need to tel the ebu which addr we mapped the nand to */
45 /* we need to tell the EBU that we have nand attached and set it up properly */
207 /* setup the EBU to run in NAND mode on our base addr */ in xway_nand_probe()
/linux/arch/mips/include/asm/mach-lantiq/
H A Dlantiq.h21 /* register access macros for EBU and CGU */
28 /* spinlock all ebu i/o */
/linux/sound/firewire/motu/
H A Dmotu-protocol-v1.c80 // 0x00104800: AES/EBU-1/2
89 // 0x00104000: AES/EBU-1
90 // 0x00104900: AES/EBU-2
91 // 0x00000060: sample rate conversion for AES/EBU input/output.
104 // 0x00000002: AES/EBU on XLR
/linux/drivers/media/test-drivers/vidtv/
H A Dvidtv_s302m.h7 * This file contains the code for an AES3 (also known as AES/EBU) encoder.
8 * It is based on EBU Tech 3250 and SMPTE 302M technical documents.
/linux/arch/mips/boot/dts/lantiq/
H A Ddanube.dtsi88 ebu0: ebu@e105300 {
89 compatible = "lantiq,ebu-xway";
/linux/Documentation/userspace-api/media/v4l/
H A Dbiblio.rst269 EBU Tech 3213
275 :author: European Broadcast Union (http://www.ebu.ch)
279 EBU Tech 3321
285 :author: European Broadcast Union (http://www.ebu.ch)
/linux/sound/firewire/fireface/
H A Dff-protocol-latter.c44 // 0x000f0000: detected rate of AES/EBU on XLR or coaxial interface
50 // 0x00000400: AES/EBU
54 // 0x00000020: Synchronized to AES/EBU on XLR or 2nd optical interface
58 // 0x00000002: Lock AES/EBU on XLR or 2nd optical interface
324 { "AES/EBU", 0x00000002, 0x00000020, }, in latter_dump_status()
/linux/sound/firewire/dice/
H A Ddice-weiss.c49 // Weiss Vesta: 192kHz 2-channel Firewire to AES/EBU interface
55 // Weiss AFI1: 192kHz 24-channel Firewire to ADAT or AES/EBU interface
/linux/drivers/mtd/maps/
H A Dlantiq-flash.c25 * The NOR flash is connected to the same external bus unit (EBU) as PCI.
27 * written to the EBU. This endianness swapping works for PCI correctly but
/linux/sound/pci/asihpi/
H A Dhpi.h171 /** Line in node - could be analog, AES/EBU or network. */
173 HPI_SOURCENODE_AESEBU_IN = 103, /**< AES/EBU input node. */
208 HPI_DESTNODE_AESEBU_OUT = 203, /**< AES/EBU output node. */
238 HPI_CONTROL_AESEBU_TRANSMITTER = 6, /**< AES/EBU transmitter control */
241 HPI_CONTROL_AESEBU_RECEIVER = 7, /**< AES/EBU receiver control. */
684 /** AES/EBU physical format - AES/EBU balanced "professional" */
686 /** AES/EBU physical format - S/PDIF unbalanced "consumer" */
690 /** AES/EBU error status bits
826 /** The adapter is clocked from a dedicated AES/EBU SampleClock input.*/
1479 /* AES/EBU Receiver control */
[all …]
/linux/drivers/spi/
H A Dspi-falcon.c40 /* EBU Clock Control Register */
315 /* set EBU clock to 100 MHz */ in falcon_sflash_setup()
319 /* set EBU clock to 50 MHz */ in falcon_sflash_setup()
/linux/arch/arm/mach-mvebu/
H A Dheadsmp-a9.S3 * SMP support: Entry point for secondary CPUs of Marvell EBU
H A Dmvebu-soc-id.h3 * Marvell EBU SoC ID and revision definitions.
/linux/drivers/memory/
H A DKconfig149 bool "Marvell EBU Device Bus Controller"
155 Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
/linux/Documentation/devicetree/bindings/clock/
H A Dmvebu-cpu-clock.txt1 Device Tree Clock bindings for cpu clock of Marvell EBU platforms
/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-mm-lantiq.txt3 By attaching hardware latches to the EBU it is possible to create output
/linux/drivers/clk/mvebu/
H A Dcommon.h3 * Marvell EBU SoC common clock handling
/linux/drivers/pci/controller/
H A DKconfig177 tristate "Marvell EBU PCIe controller"
184 Add support for Marvell EBU PCIe controller. This PCIe controller
/linux/arch/mips/include/asm/mach-lantiq/falcon/
H A Dlantiq_soc.h64 * has no EIU/EBU
/linux/sound/pcmcia/vx/
H A Dvxpocket.h45 #define VXP_CDSP_CLOCKIN_SEL_MASK 0x80 /* 0 (internal), 1 (AES/EBU) */

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