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/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer
10 #include <linux/clk-provider.h>
31 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
33 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
35 * 0ns = 0x0, 2ns = 0x1, 4n
107 meson8b_dwmac_mask_bits(struct meson8b_dwmac * dwmac,u32 reg,u32 mask,u32 value) meson8b_dwmac_mask_bits() argument
119 meson8b_dwmac_register_clk(struct meson8b_dwmac * dwmac,const char * name_suffix,const struct clk_parent_data * parents,int num_parents,const struct clk_ops * ops,struct clk_hw * hw) meson8b_dwmac_register_clk() argument
143 meson8b_init_rgmii_tx_clk(struct meson8b_dwmac * dwmac) meson8b_init_rgmii_tx_clk() argument
213 meson8b_set_phy_mode(struct meson8b_dwmac * dwmac) meson8b_set_phy_mode() argument
239 meson_axg_set_phy_mode(struct meson8b_dwmac * dwmac) meson_axg_set_phy_mode() argument
271 meson8b_devm_clk_prepare_enable(struct meson8b_dwmac * dwmac,struct clk * clk) meson8b_devm_clk_prepare_enable() argument
284 meson8b_init_rgmii_delays(struct meson8b_dwmac * dwmac) meson8b_init_rgmii_delays() argument
350 meson8b_init_prg_eth(struct meson8b_dwmac * dwmac) meson8b_init_prg_eth() argument
396 struct meson8b_dwmac *dwmac; meson8b_dwmac_probe() local
[all...]
H A Ddwmac-loongson1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Loongson-1 DWMAC glue layer
5 * Copyright (C) 2011-2023 Keguang Zhang <keguang.zhang@gmail.com>
21 /* Loongson-1 SYSCON Registers */
25 /* Loongson-
59 struct ls1x_dwmac *dwmac = plat_dat->bsp_priv; ls1b_dwmac_setup() local
86 struct ls1x_dwmac *dwmac = priv; ls1b_dwmac_syscon_init() local
140 struct ls1x_dwmac *dwmac = priv; ls1c_dwmac_syscon_init() local
170 struct ls1x_dwmac *dwmac; ls1x_dwmac_probe() local
[all...]
H A Ddwmac-visconti.c1 // SPDX-License-Identifier: GPL-2.0
25 #define ETHER_CLK_SEL_DIV_SEL_2 BIT(4)
54 struct visconti_eth *dwmac = bsp_priv;
72 return -EINVAL; in visconti_eth_set_clk_tx_rate()
76 val = readl(dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_set_clk_tx_rate()
80 writel(val, dwmac->re in visconti_eth_set_clk_tx_rate()
58 struct visconti_eth *dwmac = bsp_priv; visconti_eth_set_clk_tx_rate() local
151 struct visconti_eth *dwmac = plat_dat->bsp_priv; visconti_eth_init_hw() local
192 struct visconti_eth *dwmac = plat_dat->bsp_priv; visconti_eth_clock_probe() local
211 struct visconti_eth *dwmac = get_stmmac_bsp_priv(&pdev->dev); visconti_eth_clock_remove() local
223 struct visconti_eth *dwmac; visconti_eth_dwmac_probe() local
[all...]
/linux/Documentation/devicetree/bindings/net/
H A Dstarfive,jh7110-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: StarFive JH7110 DWMAC glue layer
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7100-dwmac
20 - starfive,jh7110-dwmac
22 - compatible
[all …]
H A Dtoshiba,visconti-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/toshiba,visconti-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba Visconti DWMAC Ethernet controller
10 - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
17 - toshiba,visconti-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
[all …]
H A Dnxp,lpc1850-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nxp,lpc1850-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
12 # We need a select here so we don't match all nodes with 'snps,dwmac'
18 - nxp,lpc1850-dwmac
20 - compatible
25 - enum:
26 - nxp,lpc1850-dwmac
[all …]
H A Dsophgo,cv1800b-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/sophgo,cv1800b-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo CV1800B DWMAC glue layer
10 - Inochi Amaoto <inochiama@gmail.com>
17 - sophgo,cv1800b-dwmac
19 - compatible
24 - const: sophgo,cv1800b-dwmac
25 - const: snps,dwmac-3.70a
[all …]
H A Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel DWMAC glue layer
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
[all …]
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/linux/arch/arm64/boot/dts/st/
H A Dstm32mp253.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&CPU_PD1>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 CPU_PD1: power-domain-cpu1 {
28 #power-domain-cells = <0>;
[all …]
H A Dstm32mp233.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&cpu1_pd>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 cpu1_pd: power-domain-cpu1 {
28 #power-domain-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
H A Dsocfpga_agilex5_socdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5";
19 stdout-path = "serial0:115200n8";
23 compatible = "gpio-leds";
25 led-0 {
45 phy-mode = "rgmii-id";
46 phy-handle = <&emac2_phy0>;
47 max-frame-size = <9000>;
50 #address-cells = <1>;
51 #size-cells = <0>;
[all …]
H A Dsocfpga_agilex3_socdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 compatible = "intel,socfpga-agilex3-socdk", "intel,socfpga-agilex3",
10 "intel,socfpga-agilex5";
18 stdout-path = "serial0:115200n8";
22 /delete-node/ cpu@2;
23 /delete-node/ cpu@3;
27 compatible = "gpio-leds";
50 phy-mode = "rgmii-id";
51 phy-handle = <&emac2_phy0>;
52 max-frame-size = <9000>;
[all …]
/linux/arch/loongarch/boot/dts/
H A Dloongson-2k1000-ref.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include "dt-bindings/thermal/thermal.h"
9 #include "loongson-2k1000.dtsi"
12 compatible = "loongson,ls2k1000-ref", "loongson,ls2k1000";
13 model = "Loongson-2K1000 Reference Board";
20 stdout-path = "serial0:115200n8";
30 reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g087.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a55";
25 next-level-cache = <&L3_CA55>;
[all …]
H A Dr9a09g077.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a55";
25 next-level-cache = <&L3_CA55>;
[all …]
/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
9 #include <dt-bindings/power/thead,th1520-power.h>
10 #include <dt-bindings/reset/thead,th1520-reset.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 timebase-frequency = <3000000>;
[all …]
/linux/arch/mips/boot/dts/loongson/
H A Dloongson1b.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
6 /dts-v1/;
10 cpu_opp_table: opp-table {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-44000000 {
15 opp-hz = /bits/ 64 <44000000>;
17 opp-47142000 {
18 opp-hz = /bits/ 64 <47142000>;
[all …]
H A Dloongson64-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 #clock-cells = <1>;
27 #clock-cells = <0>;
28 compatible = "fixed-clock";
[all …]
/linux/arch/arc/boot/dts/
H A Dabilis_tb10x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
12 compatible = "abilis,arc-tb10x";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
28 compatible = "snps,arc-timer";
30 interrupt-parent = <&intc>;
36 compatible = "snps,arc-timer";
41 #address-cells = <1>;
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dcv180x.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include "cv18xx-reset.h"
13 #address-cells = <1>;
14 #size-cells = <1>;
17 compatible = "fixed-clock";
18 clock-output-names = "osc_25m";
19 #clock-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-s4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/meson-s4-gpio.h>
10 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
11 #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
12 #include <dt-bindings/power/meson-s4-power.h>
13 #include <dt-bindings/reset/amlogic,meson-s4-reset.h>
17 #address-cells = <2>;
[all …]
/linux/arch/mips/boot/dts/ni/
H A D169445.dts1 /dts-v1/;
4 #address-cells = <1>;
5 #size-cells = <1>;
9 #address-cells = <1>;
10 #size-cells = <0>;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <50000000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_cyclone5_sodia.dts1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
12 compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga";
16 stdout-path = "serial0:115200n8";
30 compatible = "regulator-fixed";
31 regulator-name = "3.3V";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
36 leds: gpio-leds {
[all …]

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