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/linux/Documentation/devicetree/bindings/net/
H A Dstarfive,jh7110-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: StarFive JH7110 DWMAC glue layer
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7100-dwmac
20 - starfive,jh7110-dwmac
22 - compatible
[all …]
H A Dtoshiba,visconti-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/toshiba,visconti-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba Visconti DWMAC Ethernet controller
10 - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
17 - toshiba,visconti-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
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H A Dnxp,lpc1850-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nxp,lpc1850-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
12 # We need a select here so we don't match all nodes with 'snps,dwmac'
18 - nxp,lpc1850-dwmac
20 - compatible
25 - enum:
26 - nxp,lpc1850-dwmac
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H A Dsophgo,cv1800b-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/sophgo,cv1800b-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo CV1800B DWMAC glue layer
10 - Inochi Amaoto <inochiama@gmail.com>
17 - sophgo,cv1800b-dwmac
19 - compatible
24 - const: sophgo,cv1800b-dwmac
25 - const: snps,dwmac-3.70a
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H A Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel DWMAC glue layer
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
[all …]
H A Deswin,eic7700-eth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/eswin,eic7700-eth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shuang Liang <liangshuang@eswincomputing.com>
11 - Zhi Li <lizhi2@eswincomputing.com>
12 - Shangjuan Wei <weishangjuan@eswincomputing.com>
22 - eswin,eic7700-qos-eth
24 - compatible
27 - $ref: snps,dwmac.yaml#
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-nuvoton.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Nuvoton DWMAC specific glue layer
25 /* Two thousand picoseconds are evenly mapped to a 4-bit field,
42 if (of_property_read_u32(dev->of_node, property, &arg)) in nvt_gmac_get_delay()
46 return -EINVAL; in nvt_gmac_get_delay()
61 ret = nvt_gmac_get_delay(priv->dev, "rx-internal-delay-ps"); in nvt_set_phy_intf_sel()
66 ret = nvt_gmac_get_delay(priv->dev, "tx-internal-delay-ps"); in nvt_set_phy_intf_sel()
73 return -EINVAL; in nvt_set_phy_intf_sel()
76 reg = (priv->macid == 0) ? NVT_REG_SYS_GMAC0MISCR : NVT_REG_SYS_GMAC1MISCR; in nvt_set_phy_intf_sel()
77 regmap_update_bits(priv->regmap, reg, in nvt_set_phy_intf_sel()
[all …]
H A Ddwmac-motorcomm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DWMAC glue driver for Motorcomm PCI Ethernet controllers
5 * Copyright (c) 2025-2026 Yao Zi <me@ziyao.cc>
22 #define DRIVER_NAME "dwmac-motorcomm"
72 EFUSE_OP_START, priv->base + EFUSE_OP_CTRL_0); in motorcomm_efuse_read_byte()
74 ret = readl_poll_timeout(priv->base + EFUSE_OP_CTRL_1, in motorcomm_efuse_read_byte()
113 return -ENOENT; in motorcomm_efuse_get_patch_value()
120 return -ENOENT; in motorcomm_efuse_get_patch_value()
145 mac[4] = FIELD_GET(GENMASK(15, 8), maca0lr); in motorcomm_efuse_read_mac()
153 u32 reg = readl(priv->base + EPHY_CTRL); in motorcomm_deassert_mdio_phy_reset()
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/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
H A Dsocfpga_agilex5_socdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5";
19 stdout-path = "serial0:115200n8";
23 compatible = "gpio-leds";
25 led-0 {
45 phy-mode = "rgmii-id";
46 phy-handle = <&emac2_phy0>;
47 max-frame-size = <9000>;
50 #address-cells = <1>;
51 #size-cells = <0>;
[all …]
H A Dsocfpga_agilex3_socdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 compatible = "intel,socfpga-agilex3-socdk", "intel,socfpga-agilex3",
10 "intel,socfpga-agilex5";
18 stdout-path = "serial0:115200n8";
22 /delete-node/ cpu@2;
23 /delete-node/ cpu@3;
27 compatible = "gpio-leds";
50 phy-mode = "rgmii-id";
51 phy-handle = <&emac2_phy0>;
52 max-frame-size = <9000>;
[all …]
H A Dsocfpga_agilex5_socdk_013b.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 compatible = "intel,socfpga-agilex5-socdk-013b", "intel,socfpga-agilex5";
17 stdout-path = "serial0:115200n8";
21 compatible = "gpio-leds";
44 phy-mode = "rgmii-id";
45 phy-handle = <&emac2_phy0>;
46 max-frame-size = <9000>;
49 #address-cells = <1>;
50 #size-cells = <0>;
51 compatible = "snps,dwmac-mdio";
[all …]
/linux/arch/arm64/boot/dts/st/
H A Dstm32mp253.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&CPU_PD1>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 CPU_PD1: power-domain-cpu1 {
28 #power-domain-cells = <0>;
[all …]
H A Dstm32mp233.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&cpu1_pd>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 cpu1_pd: power-domain-cpu1 {
28 #power-domain-cells = <0>;
[all …]
/linux/arch/mips/boot/dts/loongson/
H A Dloongson1b.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
6 /dts-v1/;
10 cpu_opp_table: opp-table {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-44000000 {
15 opp-hz = /bits/ 64 <44000000>;
17 opp-47142000 {
18 opp-hz = /bits/ 64 <47142000>;
[all …]
H A Dloongson64-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 #clock-cells = <1>;
27 #clock-cells = <0>;
28 compatible = "fixed-clock";
[all …]
/linux/arch/arc/boot/dts/
H A Dabilis_tb10x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
12 compatible = "abilis,arc-tb10x";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
28 compatible = "snps,arc-timer";
30 interrupt-parent = <&intc>;
36 compatible = "snps,arc-timer";
41 #address-cells = <1>;
[all …]
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
[all …]
/linux/arch/mips/boot/dts/ni/
H A D169445.dts1 /dts-v1/;
4 #address-cells = <1>;
5 #size-cells = <1>;
9 #address-cells = <1>;
10 #size-cells = <0>;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <50000000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g087.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
31 #address-cells = <2>;
32 #size-cells = <2>;
33 interrupt-parent = <&gic>;
35 cluster0_opp: opp-table-0 {
36 compatible = "operating-points-v2";
38 opp-600000000 {
39 opp-hz = /bits/ 64 <600000000>;
[all …]
H A Dr9a09g077.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
31 #address-cells = <2>;
32 #size-cells = <2>;
33 interrupt-parent = <&gic>;
35 cluster0_opp: opp-table-0 {
36 compatible = "operating-points-v2";
38 opp-600000000 {
39 opp-hz = /bits/ 64 <600000000>;
[all …]
/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_cyclone5_sodia.dts1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
12 compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga";
16 stdout-path = "serial0:115200n8";
30 compatible = "regulator-fixed";
31 regulator-name = "3.3V";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
36 leds: gpio-leds {
[all …]
H A Dsocfpga_cyclone5_mercury_sa1.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
10 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
13 stdout-path = "serial0:115200n8";
20 /* Adjusted the i2c labels to use generic base-board dtsi files for
24 * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi
26 * bus in a generic base-board .dtsi file.
43 clock-frequency = <50000000>;
47 i2c-sda-hold-time-ns = <300>;
48 clock-frequency = <100000>;
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/clock/sophgo,sg2044-pll.h>
7 #include <dt-bindings/clock/sophgo,sg2044-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/pinctrl-sg2044.h>
12 #include "sg2044-cpus.dtsi"
13 #include "sg2044-reset.h"
24 compatible = "fixed-clock";
25 clock-output-names = "osc";
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dqcs404-evb-4000.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include "qcs404-evb.dtsi"
13 compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb",
20 snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
21 snps,reset-active-low;
22 snps,reset-delays-us = <0 10000 10000>;
24 pinctrl-names = "default";
25 pinctrl-0 = <&ethernet_defaults>;
[all …]

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