| /linux/drivers/iio/frequency/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 # Phase-Locked Loop (PLL) frequency synthesizers
19 Clock Generator. The driver provides direct access via sysfs.
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
37 Wideband Synthesizers. The driver provides direct access via sysfs.
48 Wideband Synthesizers. The driver provides direct access via sysfs.
65 tristate "Analog Devices ADMFM2000 Dual Microwave Down Converter"
68 Say yes here to build support for Analog Devices ADMFM2000 Dual
100 Downconverter with integrated Fractional-N PLL and VCO.
|
| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | mediatek,mtu3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
27 - mediatek,mt8186-mtu3
[all …]
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| /linux/drivers/irqchip/ |
| H A D | irq-mips-gic.c | 6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
26 #include <asm/mips-cps.h>
30 #include <dt-bindings/interrupt-controller/mips-gic.h>
44 #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
47 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
81 * Move the access lock to the next CPU's GIC local register block. in __gic_with_next_online_cpu()
98 * for_each_online_cpu_gic() - Iterate over online CPUs, access local registers
103 * access each CPUs GIC local register block, which can be accessed from the
109 for ((cpu) = __gic_with_next_online_cpu(-1); \
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| /linux/drivers/hid/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
22 most commonly used to refer to the USB-HID specification, but other
27 removed from the HID bus by the transport-layer drivers, such as
58 to work on raw hid events when they want to, and avoid using transport-specific
64 tristate "User-space I/O driver support for HID subsystem"
67 Say Y here if you want to provide HID I/O Drivers from user-space.
68 This allows to write I/O drivers in user-space and feed the data from
71 user-space device.
73 This driver cannot be used to parse HID-reports in user-space and write
74 special HID-drivers. You should use hidraw for that.
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| /linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | xilinx-xadc.txt | 16 communication. Xilinx provides a standard IP core that can be used to access the
22 - compatible: Should be one of
23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
27 * "xlnx,system-management-wiz-1.3": When using the
28 Xilinx System Management Wizard fabric IP core to access the
30 - reg: Address and length of the register set for the device
31 - interrupts: Interrupt for the XADC control interface.
32 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
33 when using the axi-xadc or the axi-system-management-wizard this must be
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| /linux/Documentation/devicetree/bindings/chrome/ |
| H A D | google,cros-ec-typec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/chrome/google,cros-ec-typec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benson Leung <bleung@chromium.org>
11 - Prashant Malani <pmalani@chromium.org>
14 Chrome OS devices have an Embedded Controller(EC) which has access to
17 cros-ec node like google,cros-ec-spi.
21 const: google,cros-ec-typec
23 '#address-cells':
[all …]
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| /linux/drivers/w1/slaves/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # 1-wire slaves configuration
6 menu "1-wire Slaves"
11 Say Y here if you want to connect 1-wire thermal sensors to your
17 Say Y here if you want to connect 1-wire
23 Say Y or M here if you want to use a DS2405 1-wire
24 single-channel addressable switch.
25 This device can also work as a single-channel
29 tristate "8-Channel Addressable Switch (IO Expander) 0x29 family support (DS2408)"
31 Say Y here if you want to use a 1-wire
[all …]
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| /linux/Documentation/fb/ |
| H A D | viafb.rst | 6 --------
15 ---------------
34 ----------------------
47 - 640x480 (default)
48 - 720x480
49 - 800x600
50 - 1024x768
53 - 8, 16, 32 (default:32)
56 - 60, 75, 85, 100, 120 (default:60)
59 - 0 : expansion (default)
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | st,stm32mp25-omm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32mp25-omm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 The STM32 Octo Memory Manager is a low-level interface that enables an
15 function map) and multiplex of single/dual/quad/octal SPI interfaces over
17 - Two single/dual/quad/octal SPI interfaces
18 - Two ports for pin assignment
22 const: st,stm32mp25-omm
[all …]
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| /linux/drivers/block/drbd/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
19 DRBD is a shared-nothing, synchronously replicated block device. It
21 clusters and in this context, is a "drop-in" replacement for shared
26 run and to access the device (/dev/drbdX). Every write is sent to
31 DRBD can also be used in dual-Primary mode (device writable on both
33 shared-nothing cluster. Needless to say, on top of dual-Primary
38 See also: https://www.drbd.org/, http://www.linux-ha.org
|
| /linux/drivers/net/ethernet/myricom/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
21 tristate "Myricom Myri-10G Ethernet support"
26 This driver supports Myricom Myri-10G Dual Protocol interface in
31 <http://www.myri.com/scs/download-Myri10GE.html>
37 bool "Direct Cache Access (DCA) Support"
41 Say Y here if you want to use Direct Cache Access (DCA) in the
|
| /linux/Documentation/driver-api/ |
| H A D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
28 called DIMM (Dual Inline Memory Module).
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
56 one 64 bits parallel access. Typically used with SDR, DDR, DDR2 and DDR3
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
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| /linux/drivers/edac/ |
| H A D | i82875p_edac.c | 13 * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
39 /* four csrows in dual channel, eight in single channel */
43 /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
64 * 9 non-DRAM lock error (ndlock)
69 * 4 AGP access outside GA
70 * 3 Invalid AGP access
79 * 9 SERR on non-DRAM lock
84 * 4 AGP access outside of GA
85 * 3 SERR on invalid AGP access
91 /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | ti,cpsw-switch.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Siddharth Vadapalli <s-vadapalli@ti.com>
11 - Roger Quadros <rogerq@kernel.org>
14 The 3-port switch gigabit ethernet subsystem provides ethernet packet
24 - const: ti,cpsw-switch
25 - items:
26 - const: ti,am335x-cpsw-switch
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|
| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | ti,timer-dm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI dual-mode timer
10 - Tony Lindgren <tony@atomide.com>
13 The TI dual-mode timer is a general purpose timer with PWM capabilities.
18 - items:
19 - enum:
20 - ti,am335x-timer
[all …]
|
| /linux/sound/soc/sof/xtensa/ |
| H A D | core.c | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
14 #include "../sof-priv.h"
23 * From 4.4.1.5 table 4-64 Exception Causes of Xtensa
34 "Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT register"},
45 "Synchronous PIF data error during LoadStore access"},
49 "Synchronous PIF address error during LoadStore access"},
89 dev_printk(level, sdev->dev, "error: DSP Firmware Oops\n"); in xtensa_dsp_oops()
91 if (xtensa_exception_causes[i].id == xoops->exccause) { in xtensa_dsp_oops()
92 dev_printk(level, sdev->dev, in xtensa_dsp_oops()
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| /linux/drivers/iio/amplifiers/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
18 AD8366 Dual-Digital Variable Gain Amplifier (VGA)
21 HMC792A 0.25 dB LSB GaAs MMIC 6-Bit Digital Attenuator
22 HMC1119 0.25 dB LSB, 7-Bit, Silicon Digital Attenuator
33 SPI Amplifier's support. The driver provides direct access via
|
| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | am335x-igep0033.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x
5 * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz
8 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
16 cpu0-supply = <&vdd1_reg>;
26 pinctrl-names = "default";
27 pinctrl-0 = <&leds_pins>;
29 compatible = "gpio-leds";
34 default-state = "on";
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|
| H A D | am335x-nano.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/
5 /dts-v1/;
15 cpu0-supply = <&dcdc2_reg>;
25 compatible = "gpio-leds";
30 default-state = "off";
36 pinctrl-names = "default";
37 pinctrl-0 = <&misc_pins>;
39 misc_pins: misc-pins {
40 pinctrl-single,pins = <
[all …]
|
| /linux/drivers/spi/ |
| H A D | spi-rspi.c | 1 // SPDX-License-Identifier: GPL-2.0
8 * Based on spi-sh.c:
21 #include <linux/dma-mapping.h>
40 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
68 /* SPCR - Control Register */
77 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
78 /* QSPI on R-Car Gen2 only */
79 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
80 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
82 /* SSLP - Slave Select Polarity Register */
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|
| /linux/Documentation/virt/hyperv/ |
| H A D | vpci.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 PCI pass-thru devices
5 In a Hyper-V guest VM, PCI pass-thru devices (also called
10 provides higher bandwidth access to the device with lower
16 Hyper-V terminology for vPCI devices is "Discrete Device
17 Assignment" (DDA). Public documentation for Hyper-V DDA is
20 …tps://learn.microsoft.com/en-us/windows-server/virtualization/hyper-v/plan/plan-for-deploying-devi…
23 and for GPUs. A similar mechanism for NICs is called SR-IOV
25 driver to interact directly with the hardware. See Hyper-V
26 public documentation here: `SR-IOV`_
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|
| /linux/drivers/misc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
27 See Documentation/misc-devices/ad525x_dpot.rst for the
40 module will be called ad525x_dpot-i2c.
51 module will be called ad525x_dpot-spi.
65 This option enables device driver support for in-band access to the
67 The ibmasm device driver allows user space application to access
78 website <https://www-03.ibm.com/systems/info/x86servers/serverproven/compat/us/>
112 UFS. Provides interface for in-kernel security controllers to access
118 tristate "TI FPC202 Dual Port Controller"
124 Dual Port Controller.
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|
| /linux/Documentation/gpu/ |
| H A D | komeda-kms.rst | 1 .. SPDX-License-Identifier: GPL-2.0
23 -----
30 ------
39 -------------------
47 --------------------------
52 -----------------------------
57 --------------------------------
62 ------
72 --------
83 - Dual display mode
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | qcom,spi-qcom-qspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 dual, or quad wire transmission modes for read/write access to slaves such
17 - $ref: /schemas/spi/spi-controller.yaml#
22 - enum:
23 - qcom,sc7180-qspi
24 - qcom,sc7280-qspi
[all …]
|
| H A D | cdns,xspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2020-21 Cadence
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Parshuram Thombare <pthombar@cadence.com>
15 single, dual, quad or octal wire transmission modes for
16 read/write access to slaves such as SPI-NOR flash.
21 - cdns,xspi-nor
22 - marvell,cn10-xspi-nor
26 - description: address and length of the controller register set
[all …]
|