dsb\-element\-size (full) in projects: linux

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Searched +full:dsb +full:- +full:element +full:- +full:size (Results 1 – 25 of 27) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/arm/
H A D	qcom,coresight-tpdm.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 4 --- 5 $id: http://devicetree.org/schemas/arm/qcom,coresight-tpdm.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Trace, Profiling and Diagnostics Monitor - TPDM 13 Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete 14 Single Bit (DSB). It performs data collection in the data producing clock 22 - Mao Jinlong <quic_jinlmao@quicinc.com> 23 - Tao Zhang <quic_taozha@quicinc.com> 31 - qcom,coresight-tpdm [all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A D	qcs615.dtsi	`1 // SPDX-License-Identifier: BSD-3-Clause 6 #include <dt-bindings/clock/qcom,qcs615-gcc.h> 7 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/dma/qcom-gpi.h> 9 #include <dt-bindings/interconnect/qcom,icc.h> 10 #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/power/qcom-rpmpd.h> 13 #include <dt-bindings/power/qcom,rpmhpd.h> 14 #include <dt-bindings/soc/qcom,rpmh-rsc.h> [all …]`
H A D	qcs8300.dtsi	`1 // SPDX-License-Identifier: BSD-3-Clause 6 #include <dt-bindings/clock/qcom,qcs8300-gcc.h> 7 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,sa8775p-camcc.h> 9 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 10 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 11 #include <dt-bindings/clock/qcom,sa8775p-videocc.h> 12 #include <dt-bindings/dma/qcom-gpi.h> 13 #include <dt-bindings/firmware/qcom,scm.h> 14 #include <dt-bindings/interconnect/qcom,icc.h> [all …]`
H A D	x1e80100.dtsi	1 // SPDX-License-Identifier: BSD-3-Clause 6 #include <dt-bindings/clock/qcom,rpmh.h> 7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 8 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h> 9 #include <dt-bindings/clock/qcom,x1e80100-gcc.h> 10 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h> 11 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h> 12 #include <dt-bindings/dma/qcom-gpi.h> 13 #include <dt-bindings/interconnect/qcom,icc.h> 14 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> [all …]
H A D	sa8775p.dtsi	1 // SPDX-License-Identifier: BSD-3-Clause 7 #include <dt-bindings/interconnect/qcom,icc.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10 #include <dt-bindings/clock/qcom,rpmh.h> 11 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 12 #include <dt-bindings/clock/qcom,sa8775p-gcc.h> 13 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 14 #include <dt-bindings/clock/qcom,sa8775p-videocc.h> 15 #include <dt-bindings/dma/qcom-gpi.h> [all …]
/illumos-gate/usr/src/data/perfmon/BDX/
H A D	broadwellx_core_v17.json	7 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last… 98 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa… 99 …-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store… 145 …"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L… 168 …"PublicDescription": "This event counts speculative cache line split store-address (STA) uops disp… 214 …event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", 237 … load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can… 283 …load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can… 305 …all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", 306 …all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", [all …]
/illumos-gate/usr/src/data/perfmon/TGL/
H A D	tigerlake_core_v1.00.json	6 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", 7 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve… 94 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit… 95 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM… 336 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store … 337 …"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or … 359 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du… 447 …y executing divide or square root operations. Accounts for integer and floating-point operations.", 469 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", 557 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", [all …]
/illumos-gate/usr/src/data/perfmon/BDW-DE/
H A D	broadwellde_core_v7.json	7 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last… 98 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa… 99 …-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store… 145 …"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L… 168 …"PublicDescription": "This event counts speculative cache line split store-address (STA) uops disp… 214 …event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", 237 … load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can… 283 …load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can… 305 …all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", 306 …all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", [all …]
/illumos-gate/usr/src/data/perfmon/SKX/
H A D	skylakex_core_v1.24.json	7 …tion. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro… 175 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/… 438 …"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path … 439 …"PublicDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path… 510 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist… 511 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio… 558 …y executing divide or square root operations. Accounts for integer and floating-point operations.", 559 …y executing divide or square root operations. Accounts for integer and floating-point operations.", 607 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", 751 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", [all …]
/illumos-gate/usr/src/data/perfmon/ICL/
H A D	icelake_core_v1.09.json	6 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", 7 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve… 98 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit… 99 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM… 351 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store … 352 …"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or … 375 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du… 467 …y executing divide or square root operations. Accounts for integer and floating-point operations.", 513 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", 628 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", [all …]
/illumos-gate/usr/src/data/perfmon/SKL/
H A D	skylake_core_v50.json	7 …tion. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro… 161 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/… 402 …"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path … 403 …"PublicDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path… 468 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist… 469 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio… 512 …y executing divide or square root operations. Accounts for integer and floating-point operations.", 513 …y executing divide or square root operations. Accounts for integer and floating-point operations.", 557 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", 689 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", [all …]
/freebsd/sys/arm64/spe/
H A D	arm_spe_backend.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 37 * SPE is enabled and configured on a per-core basis, with each core requiring 44 * - HWT allocates a large single buffer per core. This buffer is split in half 45 * to create a 2 element circular buffer (aka ping-pong buffer) where the 47 * - SMP calls are used to enable and configure each core, with SPE initially 49 * - When the first half of the buffer is full, a buffer full interrupt will 54 * - The kernel responds to HWT_IOC_BUFPTR_GET ioctl by sending details of the 56 * - The buffers pending copying will not be overwritten until an 59 * - In the case where both halfs of the buffer are full, profiling will be [all …]
/illumos-gate/usr/src/data/perfmon/BDW/
H A D	broadwell_core_v26.json	7 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last… 94 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa… 95 …-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store… 139 …"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L… 161 …"PublicDescription": "This event counts speculative cache line split store-address (STA) uops disp… 205 …event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", 227 … load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can… 271 …load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can… 292 …all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", 293 …all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", [all …]
/freebsd/contrib/opencsd/decoder/include/opencsd/
H A D	ocsd_if_types.h	41 /** VS2010 does not support inttypes - remove when VS2010 support is dropped / 64 typedef uint64_t ocsd_trc_index_t; /< Trace source index type - 64 bit size / 67 typedef uint32_t ocsd_trc_index_t; /*< Trace source index type - 32 bit size / 72 #define OCSD_BAD_TRC_INDEX ((ocsd_trc_index_t)-1) 74 #define OCSD_BAD_CS_SRC_ID ((uint8_t)-1) 99 OCSD_ERR_ATTACH_TOO_MANY, /*< Cannot attach - attach device limit reached. / 100 OCSD_ERR_ATTACH_INVALID_PARAM, /*< Cannot attach - invalid parameter. / 101 OCSD_ERR_ATTACH_COMP_NOT_FOUND,/*< Cannot detach - component not found. / 103 OCSD_ERR_RDR_FILE_NOT_FOUND, /*< source reader - file not found. / 104 OCSD_ERR_RDR_INVALID_INIT, /*< source reader - invalid initialisation parameter. / [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A D	ARMScheduleA57.td	1 //=- ARMScheduleA57.td - ARM Cortex-A57 Scheduling Defs ------ tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file defines the machine model for ARM Cortex-A57 to support 12 //===----------------------------------------------------------------------===// 14 //===----------------------------------------------------------------------===// 16 // The Cortex-A57 is a traditional superscalar microprocessor with a 17 // conservative 3-wide in-order stage for decode and dispatch. Combined with the 18 // much wider out-of-order issue stage, this produced a need to carefully 19 // schedule micro-ops so that all three decoded each cycle are successfully [all …]
H A D	ARMInstrInfo.td	1 //===- ARMInstrInfo.td - Target Description for ARM Target -- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===// 27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 85 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 257 // VDUPLANE can produce a quad-register result from a double-register source, 313 // reinterprets the _register_ format - and in big-endian, the memory and 318 // whereas 'bitconvert' will map it to the high byte in big-endian mode, [all …]
H A D	ARMISelLowering.cpp	1 //===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 122 #define DEBUG_TYPE "arm-isel" 131 ARMInterworking("arm-interworking", cl::Hidden, 136 "arm-promote-constant", cl::Hidden, 141 "arm-promote-constant-max-size", cl::Hidden, 142 cl::desc("Maximum size of constant to promote into a constant pool"), 145 "arm-promote-constant-max-total", cl::Hidden, [all …]
H A D	ARMInstrThumb2.td	1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 32 // (asr or lsl). The 6-bit immediate encodes as: 35 // {4-0} imm5 shift amount. 72 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value 74 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N), 78 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value 80 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), SDLoc(N), [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A D	AArch64AsmParser.cpp	1 //==- AArch64AsmParser.cpp - Parse AArch64 assembly to MCInst instructions -==// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 109 "No destructive element size set for movprfx"); in CreateFromInst() 121 "No destructive element size set for movprfx"); in CreateFromInst() 238 /// @name Auto-generated Match Functions 309 // Alias .hword/.word/.[dx]word to the target-independent in AArch64AsmParser() 341 /// AArch64Operand - Instances of this class represent a parsed AArch64 machine 591 /// getStartLoc - Get the location of the first token of this operand. 593 /// getEndLoc - Get the location of the last token of this operand. [all …]
/freebsd/sys/contrib/vchiq/interface/vchiq_arm/
H A D	vchiq_core.c	2 * Copyright (c) 2010-2012 Broadcom. All rights reserved. 13 * 3. The names of the above-listed copyright holders may not be used 41 #define SLOT_INFO_FROM_INDEX(state, index) (state->slot_info + (index)) 42 #define SLOT_DATA_FROM_INDEX(state, index) (state->slot_data + (index)) 44 (((unsigned int)((char )data - (char )state->slot_data)) / \ 47 ((unsigned int)(info - state->slot_info)) 51 #define BULK_INDEX(x) (x & (VCHIQ_NUM_SERVICE_BULKS - 1)) 54 (((srv) && (srv)->trace) ? VCHIQ_LOG_TRACE : vchiq_core_msg_log_level) 56 (((srv) && (srv)->trace) \|\| (vchiq_core_msg_log_level >= (lev))) 170 vchiq_log_info(vchiq_core_log_level, "%d: srv:%d %s->%s", in vchiq_set_service_state() [all …]
/freebsd/sys/conf/
H A D	NOTES	2 # NOTES -- Lines that can be cut/pasted into kernel and hints configs. 11 # Please use ``make LINT'' to create an old-style LINT file if you want to 12 # do kernel test-builds. 48 # auto-size based on physical memory. 66 # after most other flags. Here we use it to inhibit use of non-optimal 67 # gcc built-in functions (e.g., memcmp). 70 # The following is equivalent to 'config -g KERNELNAME' and creates 71 # 'kernel.debug' compiled with -g debugging as well as a normal 81 makeoptions CONF_CFLAGS=-fno-builtin #Don't allow use of memcmp, etc. 82 #makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A D	ARMAsmParser.cpp	1 //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 71 #define DEBUG_TYPE "asm-parser" 81 "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly), 92 static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes", 101 // of Mask, and so on downwards. So (5 - Position) will shift the in extractITMaskBit() 102 // right bit down to bit 0, including the always-0 bit at bit 4 for in extractITMaskBit() 104 return (Mask >> (5 - Position) & 1); in extractITMaskBit() 159 if (PI != PE && (PII == PIE \|\| PI->getPointer() < PII->getPointer())) in emitPersonalityLocNotes() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A D	AArch64InstrInfo.td	1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 14 //===----------------------------------------------------------------------===// 21 def HasV8_0a : Predicate<"Subtarget->hasV8_0aOps()">, 23 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, 25 def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, 27 def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, 29 def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, [all …]
H A D	AArch64InstrInfo.cpp	1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 67 "aarch64-tbz-offset-bits", cl::Hidden, cl::init(14), 71 "aarch64-cbz-offset-bits", cl::Hidden, cl::init(19), 75 BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19), 79 BDisplacementBits("aarch64-b-offset-bits", cl::Hidden, cl::init(26), 87 /// GetInstSize - Return the number of bytes of code the specified 92 const Function &F = MF->getFunction(); in getInstSizeInBytes() [all …]
/illumos-gate/usr/src/data/perfmon/CLX/
H A D	cascadelakex_core_v1.11.json	7 …tion. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro… 175 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/… 414 …"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path … 415 …"PublicDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path… 486 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist… 487 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio… 534 …y executing divide or square root operations. Accounts for integer and floating-point operations.", 535 …y executing divide or square root operations. Accounts for integer and floating-point operations.", 583 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", 727 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", [all …]