1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,qcs615-gcc.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/dma/qcom-gpi.h> 9#include <dt-bindings/interconnect/qcom,icc.h> 10#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/power/qcom,rpmhpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <2>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a55"; 28 reg = <0x0 0x0>; 29 enable-method = "psci"; 30 power-domains = <&cpu_pd0>; 31 power-domain-names = "psci"; 32 capacity-dmips-mhz = <1024>; 33 dynamic-power-coefficient = <100>; 34 next-level-cache = <&l2_0>; 35 #cooling-cells = <2>; 36 37 l2_0: l2-cache { 38 compatible = "cache"; 39 cache-level = <2>; 40 cache-unified; 41 next-level-cache = <&l3_0>; 42 }; 43 }; 44 45 cpu1: cpu@100 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a55"; 48 reg = <0x0 0x100>; 49 enable-method = "psci"; 50 power-domains = <&cpu_pd1>; 51 power-domain-names = "psci"; 52 capacity-dmips-mhz = <1024>; 53 dynamic-power-coefficient = <100>; 54 next-level-cache = <&l2_100>; 55 56 l2_100: l2-cache { 57 compatible = "cache"; 58 cache-level = <2>; 59 cache-unified; 60 next-level-cache = <&l3_0>; 61 }; 62 }; 63 64 cpu2: cpu@200 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a55"; 67 reg = <0x0 0x200>; 68 enable-method = "psci"; 69 power-domains = <&cpu_pd2>; 70 power-domain-names = "psci"; 71 capacity-dmips-mhz = <1024>; 72 dynamic-power-coefficient = <100>; 73 next-level-cache = <&l2_200>; 74 75 l2_200: l2-cache { 76 compatible = "cache"; 77 cache-level = <2>; 78 cache-unified; 79 next-level-cache = <&l3_0>; 80 }; 81 }; 82 83 cpu3: cpu@300 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a55"; 86 reg = <0x0 0x300>; 87 enable-method = "psci"; 88 power-domains = <&cpu_pd3>; 89 power-domain-names = "psci"; 90 capacity-dmips-mhz = <1024>; 91 dynamic-power-coefficient = <100>; 92 next-level-cache = <&l2_300>; 93 94 l2_300: l2-cache { 95 compatible = "cache"; 96 cache-level = <2>; 97 cache-unified; 98 next-level-cache = <&l3_0>; 99 }; 100 }; 101 102 cpu4: cpu@400 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a55"; 105 reg = <0x0 0x400>; 106 enable-method = "psci"; 107 power-domains = <&cpu_pd4>; 108 power-domain-names = "psci"; 109 capacity-dmips-mhz = <1024>; 110 dynamic-power-coefficient = <100>; 111 next-level-cache = <&l2_400>; 112 113 l2_400: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-unified; 117 next-level-cache = <&l3_0>; 118 }; 119 }; 120 121 cpu5: cpu@500 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a55"; 124 reg = <0x0 0x500>; 125 enable-method = "psci"; 126 power-domains = <&cpu_pd5>; 127 power-domain-names = "psci"; 128 capacity-dmips-mhz = <1024>; 129 dynamic-power-coefficient = <100>; 130 next-level-cache = <&l2_500>; 131 132 l2_500: l2-cache { 133 compatible = "cache"; 134 cache-level = <2>; 135 cache-unified; 136 next-level-cache = <&l3_0>; 137 }; 138 }; 139 140 cpu6: cpu@600 { 141 device_type = "cpu"; 142 compatible = "arm,cortex-a76"; 143 reg = <0x0 0x600>; 144 enable-method = "psci"; 145 power-domains = <&cpu_pd6>; 146 power-domain-names = "psci"; 147 capacity-dmips-mhz = <1740>; 148 dynamic-power-coefficient = <404>; 149 next-level-cache = <&l2_600>; 150 #cooling-cells = <2>; 151 152 l2_600: l2-cache { 153 compatible = "cache"; 154 cache-level = <2>; 155 cache-unified; 156 next-level-cache = <&l3_0>; 157 }; 158 }; 159 160 cpu7: cpu@700 { 161 device_type = "cpu"; 162 compatible = "arm,cortex-a76"; 163 reg = <0x0 0x700>; 164 enable-method = "psci"; 165 power-domains = <&cpu_pd7>; 166 power-domain-names = "psci"; 167 capacity-dmips-mhz = <1740>; 168 dynamic-power-coefficient = <404>; 169 next-level-cache = <&l2_700>; 170 171 l2_700: l2-cache { 172 compatible = "cache"; 173 cache-level = <2>; 174 cache-unified; 175 next-level-cache = <&l3_0>; 176 }; 177 }; 178 179 cpu-map { 180 cluster0 { 181 core0 { 182 cpu = <&cpu0>; 183 }; 184 185 core1 { 186 cpu = <&cpu1>; 187 }; 188 189 core2 { 190 cpu = <&cpu2>; 191 }; 192 193 core3 { 194 cpu = <&cpu3>; 195 }; 196 197 core4 { 198 cpu = <&cpu4>; 199 }; 200 201 core5 { 202 cpu = <&cpu5>; 203 }; 204 205 core6 { 206 cpu = <&cpu6>; 207 }; 208 209 core7 { 210 cpu = <&cpu7>; 211 }; 212 }; 213 }; 214 215 l3_0: l3-cache { 216 compatible = "cache"; 217 cache-level = <3>; 218 cache-unified; 219 }; 220 }; 221 222 dummy_eud: dummy-sink { 223 compatible = "arm,coresight-dummy-sink"; 224 225 in-ports { 226 port { 227 eud_in: endpoint { 228 remote-endpoint = <&replicator_swao_out1>; 229 }; 230 }; 231 }; 232 }; 233 234 idle-states { 235 entry-method = "psci"; 236 237 little_cpu_sleep_0: cpu-sleep-0-0 { 238 compatible = "arm,idle-state"; 239 idle-state-name = "silver-power-collapse"; 240 arm,psci-suspend-param = <0x40000003>; 241 entry-latency-us = <549>; 242 exit-latency-us = <901>; 243 min-residency-us = <1774>; 244 local-timer-stop; 245 }; 246 247 little_cpu_sleep_1: cpu-sleep-0-1 { 248 compatible = "arm,idle-state"; 249 idle-state-name = "silver-rail-power-collapse"; 250 arm,psci-suspend-param = <0x40000004>; 251 entry-latency-us = <702>; 252 exit-latency-us = <915>; 253 min-residency-us = <4001>; 254 local-timer-stop; 255 }; 256 257 big_cpu_sleep_0: cpu-sleep-1-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "gold-power-collapse"; 260 arm,psci-suspend-param = <0x40000003>; 261 entry-latency-us = <523>; 262 exit-latency-us = <1244>; 263 min-residency-us = <2207>; 264 local-timer-stop; 265 }; 266 267 big_cpu_sleep_1: cpu-sleep-1-1 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "gold-rail-power-collapse"; 270 arm,psci-suspend-param = <0x40000004>; 271 entry-latency-us = <526>; 272 exit-latency-us = <1854>; 273 min-residency-us = <5555>; 274 local-timer-stop; 275 }; 276 }; 277 278 domain-idle-states { 279 cluster_sleep_0: cluster-sleep-0 { 280 compatible = "domain-idle-state"; 281 arm,psci-suspend-param = <0x41000044>; 282 entry-latency-us = <2752>; 283 exit-latency-us = <3048>; 284 min-residency-us = <6118>; 285 }; 286 287 cluster_sleep_1: cluster-sleep-1 { 288 compatible = "domain-idle-state"; 289 arm,psci-suspend-param = <0x41001344>; 290 entry-latency-us = <3263>; 291 exit-latency-us = <4562>; 292 min-residency-us = <8467>; 293 }; 294 295 cluster_sleep_2: cluster-sleep-2 { 296 compatible = "domain-idle-state"; 297 arm,psci-suspend-param = <0x4100b344>; 298 entry-latency-us = <3638>; 299 exit-latency-us = <6562>; 300 min-residency-us = <9826>; 301 }; 302 }; 303 304 memory@80000000 { 305 device_type = "memory"; 306 /* We expect the bootloader to fill in the size */ 307 reg = <0 0x80000000 0 0>; 308 }; 309 310 firmware { 311 scm { 312 compatible = "qcom,scm-qcs615", "qcom,scm"; 313 qcom,dload-mode = <&tcsr 0x13000>; 314 }; 315 }; 316 317 camnoc_virt: interconnect-0 { 318 compatible = "qcom,qcs615-camnoc-virt"; 319 #interconnect-cells = <2>; 320 qcom,bcm-voters = <&apps_bcm_voter>; 321 }; 322 323 ipa_virt: interconnect-1 { 324 compatible = "qcom,qcs615-ipa-virt"; 325 #interconnect-cells = <2>; 326 qcom,bcm-voters = <&apps_bcm_voter>; 327 }; 328 329 mc_virt: interconnect-2 { 330 compatible = "qcom,qcs615-mc-virt"; 331 #interconnect-cells = <2>; 332 qcom,bcm-voters = <&apps_bcm_voter>; 333 }; 334 335 smp2p-adsp { 336 compatible = "qcom,smp2p"; 337 qcom,smem = <443>, <429>; 338 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 339 /* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */ 340 mboxes = <&apss_shared 26>; 341 342 qcom,local-pid = <0>; 343 qcom,remote-pid = <2>; 344 345 adsp_smp2p_out: master-kernel { 346 qcom,entry-name = "master-kernel"; 347 #qcom,smem-state-cells = <1>; 348 }; 349 350 adsp_smp2p_in: slave-kernel { 351 qcom,entry-name = "slave-kernel"; 352 interrupt-controller; 353 #interrupt-cells = <2>; 354 }; 355 }; 356 357 smp2p-cdsp { 358 compatible = "qcom,smp2p"; 359 qcom,smem = <94>, <432>; 360 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 361 mboxes = <&apss_shared 6>; 362 363 qcom,local-pid = <0>; 364 qcom,remote-pid = <5>; 365 366 cdsp_smp2p_out: master-kernel { 367 qcom,entry-name = "master-kernel"; 368 #qcom,smem-state-cells = <1>; 369 }; 370 371 cdsp_smp2p_in: slave-kernel { 372 qcom,entry-name = "slave-kernel"; 373 interrupt-controller; 374 #interrupt-cells = <2>; 375 }; 376 377 }; 378 379 qup_opp_table: opp-table-qup { 380 compatible = "operating-points-v2"; 381 opp-shared; 382 383 opp-75000000 { 384 opp-hz = /bits/ 64 <75000000>; 385 required-opps = <&rpmhpd_opp_low_svs>; 386 }; 387 388 opp-100000000 { 389 opp-hz = /bits/ 64 <100000000>; 390 required-opps = <&rpmhpd_opp_svs>; 391 }; 392 393 opp-128000000 { 394 opp-hz = /bits/ 64 <128000000>; 395 required-opps = <&rpmhpd_opp_nom>; 396 }; 397 }; 398 399 psci { 400 compatible = "arm,psci-1.0"; 401 method = "smc"; 402 403 cpu_pd0: power-domain-cpu0 { 404 #power-domain-cells = <0>; 405 power-domains = <&cluster_pd>; 406 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 407 }; 408 409 cpu_pd1: power-domain-cpu1 { 410 #power-domain-cells = <0>; 411 power-domains = <&cluster_pd>; 412 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 413 }; 414 415 cpu_pd2: power-domain-cpu2 { 416 #power-domain-cells = <0>; 417 power-domains = <&cluster_pd>; 418 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 419 }; 420 421 cpu_pd3: power-domain-cpu3 { 422 #power-domain-cells = <0>; 423 power-domains = <&cluster_pd>; 424 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 425 }; 426 427 cpu_pd4: power-domain-cpu4 { 428 #power-domain-cells = <0>; 429 power-domains = <&cluster_pd>; 430 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 431 }; 432 433 cpu_pd5: power-domain-cpu5 { 434 #power-domain-cells = <0>; 435 power-domains = <&cluster_pd>; 436 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 437 }; 438 439 cpu_pd6: power-domain-cpu6 { 440 #power-domain-cells = <0>; 441 power-domains = <&cluster_pd>; 442 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 443 }; 444 445 cpu_pd7: power-domain-cpu7 { 446 #power-domain-cells = <0>; 447 power-domains = <&cluster_pd>; 448 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 449 }; 450 451 cluster_pd: power-domain-cluster { 452 #power-domain-cells = <0>; 453 domain-idle-states = <&cluster_sleep_0 454 &cluster_sleep_1 455 &cluster_sleep_2>; 456 }; 457 }; 458 459 reserved-memory { 460 #address-cells = <2>; 461 #size-cells = <2>; 462 ranges; 463 464 aop_cmd_db_mem: aop-cmd-db@85f20000 { 465 compatible = "qcom,cmd-db"; 466 reg = <0x0 0x85f20000 0x0 0x20000>; 467 no-map; 468 }; 469 470 smem_region: smem@86000000 { 471 compatible = "qcom,smem"; 472 reg = <0x0 0x86000000 0x0 0x200000>; 473 no-map; 474 hwlocks = <&tcsr_mutex 3>; 475 }; 476 477 rproc_cdsp_mem: rproc-cdsp@93b00000 { 478 reg = <0x0 0x93b00000 0x0 0x1e00000>; 479 no-map; 480 }; 481 482 rproc_adsp_mem: rproc-adsp@95900000 { 483 reg = <0x0 0x95900000 0x0 0x1e00000>; 484 no-map; 485 }; 486 }; 487 488 soc: soc@0 { 489 compatible = "simple-bus"; 490 ranges = <0 0 0 0 0x10 0>; 491 dma-ranges = <0 0 0 0 0x10 0>; 492 #address-cells = <2>; 493 #size-cells = <2>; 494 495 gcc: clock-controller@100000 { 496 compatible = "qcom,qcs615-gcc"; 497 reg = <0 0x00100000 0 0x1f0000>; 498 499 #clock-cells = <1>; 500 #reset-cells = <1>; 501 #power-domain-cells = <1>; 502 }; 503 504 qfprom: efuse@780000 { 505 compatible = "qcom,qcs615-qfprom", "qcom,qfprom"; 506 reg = <0x0 0x00780000 0x0 0x7000>; 507 #address-cells = <1>; 508 #size-cells = <1>; 509 510 qusb2_hstx_trim: hstx-trim@1f8 { 511 reg = <0x1fb 0x1>; 512 bits = <1 4>; 513 }; 514 }; 515 516 rng@793000 { 517 compatible = "qcom,qcs615-trng", "qcom,trng"; 518 reg = <0x0 0x00793000 0x0 0x1000>; 519 }; 520 521 sdhc_1: mmc@7c4000 { 522 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 523 reg = <0x0 0x007c4000 0x0 0x1000>, 524 <0x0 0x007c5000 0x0 0x1000>, 525 <0x0 0x007c8000 0x0 0x8000>; 526 reg-names = "hc", 527 "cqhci", 528 "ice"; 529 530 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 532 interrupt-names = "hc_irq", 533 "pwr_irq"; 534 535 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 536 <&gcc GCC_SDCC1_APPS_CLK>, 537 <&rpmhcc RPMH_CXO_CLK>, 538 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 539 clock-names = "iface", 540 "core", 541 "xo", 542 "ice"; 543 544 resets = <&gcc GCC_SDCC1_BCR>; 545 546 power-domains = <&rpmhpd RPMHPD_CX>; 547 operating-points-v2 = <&sdhc1_opp_table>; 548 iommus = <&apps_smmu 0x02c0 0x0>; 549 interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS 550 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 551 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 552 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 553 interconnect-names = "sdhc-ddr", 554 "cpu-sdhc"; 555 556 qcom,dll-config = <0x000f642c>; 557 qcom,ddr-config = <0x80040868>; 558 supports-cqe; 559 dma-coherent; 560 561 status = "disabled"; 562 563 sdhc1_opp_table: opp-table { 564 compatible = "operating-points-v2"; 565 566 opp-50000000 { 567 opp-hz = /bits/ 64 <50000000>; 568 required-opps = <&rpmhpd_opp_low_svs>; 569 }; 570 571 opp-100000000 { 572 opp-hz = /bits/ 64 <100000000>; 573 required-opps = <&rpmhpd_opp_svs>; 574 }; 575 576 opp-200000000 { 577 opp-hz = /bits/ 64 <200000000>; 578 required-opps = <&rpmhpd_opp_svs_l1>; 579 }; 580 581 opp-384000000 { 582 opp-hz = /bits/ 64 <384000000>; 583 required-opps = <&rpmhpd_opp_nom>; 584 }; 585 }; 586 }; 587 588 gpi_dma0: dma-controller@800000 { 589 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 590 reg = <0x0 0x800000 0x0 0x60000>; 591 #dma-cells = <3>; 592 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 600 dma-channels = <8>; 601 dma-channel-mask = <0xf>; 602 iommus = <&apps_smmu 0xd6 0x0>; 603 status = "disabled"; 604 }; 605 606 qupv3_id_0: geniqup@8c0000 { 607 compatible = "qcom,geni-se-qup"; 608 reg = <0x0 0x008c0000 0x0 0x6000>; 609 ranges; 610 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 611 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 612 clock-names = "m-ahb", 613 "s-ahb"; 614 iommus = <&apps_smmu 0xc3 0x0>; 615 #address-cells = <2>; 616 #size-cells = <2>; 617 status = "disabled"; 618 619 uart0: serial@880000 { 620 compatible = "qcom,geni-debug-uart"; 621 reg = <0x0 0x00880000 0x0 0x4000>; 622 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 623 clock-names = "se"; 624 pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>; 625 pinctrl-names = "default"; 626 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 627 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 628 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 629 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 630 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 631 interconnect-names = "qup-core", 632 "qup-config"; 633 power-domains = <&rpmhpd RPMHPD_CX>; 634 status = "disabled"; 635 }; 636 637 i2c1: i2c@884000 { 638 compatible = "qcom,geni-i2c"; 639 reg = <0x0 0x884000 0x0 0x4000>; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 644 clock-names = "se"; 645 pinctrl-0 = <&qup_i2c1_data_clk>; 646 pinctrl-names = "default"; 647 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 648 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 649 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 650 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 651 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 652 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 653 interconnect-names = "qup-core", 654 "qup-config", 655 "qup-memory"; 656 power-domains = <&rpmhpd RPMHPD_CX>; 657 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 658 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 659 dma-names = "tx", 660 "rx"; 661 status = "disabled"; 662 }; 663 664 i2c2: i2c@888000 { 665 compatible = "qcom,geni-i2c"; 666 reg = <0x0 0x888000 0x0 0x4000>; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 671 clock-names = "se"; 672 pinctrl-0 = <&qup_i2c2_data_clk>; 673 pinctrl-names = "default"; 674 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 675 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 676 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 677 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 678 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 679 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 680 interconnect-names = "qup-core", 681 "qup-config", 682 "qup-memory"; 683 power-domains = <&rpmhpd RPMHPD_CX>; 684 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 685 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 686 dma-names = "tx", 687 "rx"; 688 status = "disabled"; 689 }; 690 691 spi2: spi@888000 { 692 compatible = "qcom,geni-spi"; 693 reg = <0x0 0x00888000 0x0 0x4000>; 694 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 696 clock-names = "se"; 697 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 698 pinctrl-names = "default"; 699 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 700 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 701 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 702 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 703 interconnect-names = "qup-core", 704 "qup-config"; 705 power-domains = <&rpmhpd RPMHPD_CX>; 706 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 707 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 708 dma-names = "tx", 709 "rx"; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 status = "disabled"; 713 }; 714 715 uart2: serial@888000 { 716 compatible = "qcom,geni-uart"; 717 reg = <0x0 0x00888000 0x0 0x4000>; 718 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 720 clock-names = "se"; 721 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 722 <&qup_uart2_tx>, <&qup_uart2_rx>; 723 pinctrl-names = "default"; 724 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 725 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 726 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 727 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 728 interconnect-names = "qup-core", 729 "qup-config"; 730 power-domains = <&rpmhpd RPMHPD_CX>; 731 status = "disabled"; 732 }; 733 734 i2c3: i2c@88c000 { 735 compatible = "qcom,geni-i2c"; 736 reg = <0x0 0x88c000 0x0 0x4000>; 737 #address-cells = <1>; 738 #size-cells = <0>; 739 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 741 clock-names = "se"; 742 pinctrl-0 = <&qup_i2c3_data_clk>; 743 pinctrl-names = "default"; 744 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 745 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 746 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 747 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 748 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 749 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 750 interconnect-names = "qup-core", 751 "qup-config", 752 "qup-memory"; 753 power-domains = <&rpmhpd RPMHPD_CX>; 754 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 755 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 756 dma-names = "tx", 757 "rx"; 758 status = "disabled"; 759 }; 760 }; 761 762 gpi_dma1: dma-controller@a00000 { 763 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 764 reg = <0x0 0xa00000 0x0 0x60000>; 765 #dma-cells = <3>; 766 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 774 dma-channels = <8>; 775 dma-channel-mask = <0xf>; 776 iommus = <&apps_smmu 0x376 0x0>; 777 status = "disabled"; 778 }; 779 780 qupv3_id_1: geniqup@ac0000 { 781 compatible = "qcom,geni-se-qup"; 782 reg = <0x0 0xac0000 0x0 0x2000>; 783 ranges; 784 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 785 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 786 clock-names = "m-ahb", 787 "s-ahb"; 788 iommus = <&apps_smmu 0x363 0x0>; 789 #address-cells = <2>; 790 #size-cells = <2>; 791 status = "disabled"; 792 793 i2c4: i2c@a80000 { 794 compatible = "qcom,geni-i2c"; 795 reg = <0x0 0xa80000 0x0 0x4000>; 796 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 797 clock-names = "se"; 798 pinctrl-0 = <&qup_i2c4_data_clk>; 799 pinctrl-names = "default"; 800 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 804 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 805 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 806 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 807 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 808 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 809 interconnect-names = "qup-core", 810 "qup-config", 811 "qup-memory"; 812 power-domains = <&rpmhpd RPMHPD_CX>; 813 required-opps = <&rpmhpd_opp_low_svs>; 814 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 815 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 816 dma-names = "tx", 817 "rx"; 818 status = "disabled"; 819 }; 820 821 spi4: spi@a80000 { 822 compatible = "qcom,geni-spi"; 823 reg = <0x0 0xa80000 0x0 0x4000>; 824 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 825 clock-names = "se"; 826 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 827 pinctrl-names = "default"; 828 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 832 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 833 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 834 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 835 interconnect-names = "qup-core", 836 "qup-config"; 837 power-domains = <&rpmhpd RPMHPD_CX>; 838 operating-points-v2 = <&qup_opp_table>; 839 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 840 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 841 dma-names = "tx", 842 "rx"; 843 status = "disabled"; 844 }; 845 846 uart4: serial@a80000 { 847 compatible = "qcom,geni-uart"; 848 reg = <0x0 0xa80000 0x0 0x4000>; 849 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 850 clock-names = "se"; 851 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 852 <&qup_uart4_tx>, <&qup_uart4_rx>; 853 pinctrl-names = "default"; 854 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 855 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 856 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 857 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 858 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 859 interconnect-names = "qup-core", 860 "qup-config"; 861 power-domains = <&rpmhpd RPMHPD_CX>; 862 operating-points-v2 = <&qup_opp_table>; 863 status = "disabled"; 864 }; 865 866 i2c5: i2c@a84000 { 867 compatible = "qcom,geni-i2c"; 868 reg = <0x0 0xa84000 0x0 0x4000>; 869 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 870 clock-names = "se"; 871 pinctrl-0 = <&qup_i2c5_data_clk>; 872 pinctrl-names = "default"; 873 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 877 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 878 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 879 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 880 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 881 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 882 interconnect-names = "qup-core", 883 "qup-config", 884 "qup-memory"; 885 power-domains = <&rpmhpd RPMHPD_CX>; 886 required-opps = <&rpmhpd_opp_low_svs>; 887 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 888 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 889 dma-names = "tx", 890 "rx"; 891 status = "disabled"; 892 }; 893 894 i2c6: i2c@a88000 { 895 compatible = "qcom,geni-i2c"; 896 reg = <0x0 0xa88000 0x0 0x4000>; 897 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 898 clock-names = "se"; 899 pinctrl-0 = <&qup_i2c6_data_clk>; 900 pinctrl-names = "default"; 901 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 905 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 906 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 907 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 908 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 909 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 910 interconnect-names = "qup-core", 911 "qup-config", 912 "qup-memory"; 913 power-domains = <&rpmhpd RPMHPD_CX>; 914 required-opps = <&rpmhpd_opp_low_svs>; 915 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 916 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 917 dma-names = "tx", 918 "rx"; 919 status = "disabled"; 920 }; 921 922 spi6: spi@a88000 { 923 compatible = "qcom,geni-spi"; 924 reg = <0x0 0xa88000 0x0 0x4000>; 925 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 926 clock-names = "se"; 927 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 928 pinctrl-names = "default"; 929 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 933 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 934 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 935 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 936 interconnect-names = "qup-core", 937 "qup-config"; 938 power-domains = <&rpmhpd RPMHPD_CX>; 939 operating-points-v2 = <&qup_opp_table>; 940 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 941 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 942 dma-names = "tx", 943 "rx"; 944 status = "disabled"; 945 }; 946 947 uart6: serial@a88000 { 948 compatible = "qcom,geni-uart"; 949 reg = <0x0 0xa88000 0x0 0x4000>; 950 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 951 clock-names = "se"; 952 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 953 <&qup_uart6_tx>, <&qup_uart6_rx>; 954 pinctrl-names = "default"; 955 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 956 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 957 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 958 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 959 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 960 interconnect-names = "qup-core", 961 "qup-config"; 962 power-domains = <&rpmhpd RPMHPD_CX>; 963 operating-points-v2 = <&qup_opp_table>; 964 status = "disabled"; 965 }; 966 967 i2c7: i2c@a8c000 { 968 compatible = "qcom,geni-i2c"; 969 reg = <0x0 0xa8c000 0x0 0x4000>; 970 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 971 clock-names = "se"; 972 pinctrl-0 = <&qup_i2c7_data_clk>; 973 pinctrl-names = "default"; 974 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 975 #address-cells = <1>; 976 #size-cells = <0>; 977 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 978 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 979 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 980 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 981 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 982 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 983 interconnect-names = "qup-core", 984 "qup-config", 985 "qup-memory"; 986 power-domains = <&rpmhpd RPMHPD_CX>; 987 required-opps = <&rpmhpd_opp_low_svs>; 988 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 989 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 990 dma-names = "tx", 991 "rx"; 992 status = "disabled"; 993 }; 994 995 spi7: spi@a8c000 { 996 compatible = "qcom,geni-spi"; 997 reg = <0x0 0xa8c000 0x0 0x4000>; 998 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 999 clock-names = "se"; 1000 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1001 pinctrl-names = "default"; 1002 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1006 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1007 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1008 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1009 interconnect-names = "qup-core", 1010 "qup-config"; 1011 power-domains = <&rpmhpd RPMHPD_CX>; 1012 operating-points-v2 = <&qup_opp_table>; 1013 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1014 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1015 dma-names = "tx", 1016 "rx"; 1017 status = "disabled"; 1018 }; 1019 1020 uart7: serial@a8c000 { 1021 compatible = "qcom,geni-uart"; 1022 reg = <0x0 0xa8c000 0x0 0x4000>; 1023 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1024 clock-names = "se"; 1025 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, 1026 <&qup_uart7_tx>, <&qup_uart7_rx>; 1027 pinctrl-names = "default"; 1028 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1029 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1030 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1031 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1032 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1033 interconnect-names = "qup-core", 1034 "qup-config"; 1035 power-domains = <&rpmhpd RPMHPD_CX>; 1036 operating-points-v2 = <&qup_opp_table>; 1037 status = "disabled"; 1038 }; 1039 }; 1040 1041 config_noc: interconnect@1500000 { 1042 reg = <0x0 0x01500000 0x0 0x5080>; 1043 compatible = "qcom,qcs615-config-noc"; 1044 #interconnect-cells = <2>; 1045 qcom,bcm-voters = <&apps_bcm_voter>; 1046 }; 1047 1048 system_noc: interconnect@1620000 { 1049 reg = <0x0 0x01620000 0x0 0x1f300>; 1050 compatible = "qcom,qcs615-system-noc"; 1051 #interconnect-cells = <2>; 1052 qcom,bcm-voters = <&apps_bcm_voter>; 1053 }; 1054 1055 aggre1_noc: interconnect@1700000 { 1056 reg = <0x0 0x01700000 0x0 0x3f200>; 1057 compatible = "qcom,qcs615-aggre1-noc"; 1058 #interconnect-cells = <2>; 1059 qcom,bcm-voters = <&apps_bcm_voter>; 1060 }; 1061 1062 mmss_noc: interconnect@1740000 { 1063 reg = <0x0 0x01740000 0x0 0x1c100>; 1064 compatible = "qcom,qcs615-mmss-noc"; 1065 #interconnect-cells = <2>; 1066 qcom,bcm-voters = <&apps_bcm_voter>; 1067 }; 1068 1069 ufs_mem_hc: ufshc@1d84000 { 1070 compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1071 reg = <0x0 0x01d84000 0x0 0x3000>, 1072 <0x0 0x01d90000 0x0 0x8000>; 1073 reg-names = "std", 1074 "ice"; 1075 1076 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1077 1078 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1079 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1080 <&gcc GCC_UFS_PHY_AHB_CLK>, 1081 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1082 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, 1083 <&rpmhcc RPMH_CXO_CLK>, 1084 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1085 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; 1086 clock-names = "core_clk", 1087 "bus_aggr_clk", 1088 "iface_clk", 1089 "core_clk_unipro", 1090 "ref_clk", 1091 "tx_lane0_sync_clk", 1092 "rx_lane0_sync_clk", 1093 "ice_core_clk"; 1094 1095 resets = <&gcc GCC_UFS_PHY_BCR>; 1096 reset-names = "rst"; 1097 1098 operating-points-v2 = <&ufs_opp_table>; 1099 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1100 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1101 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1102 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 1103 interconnect-names = "ufs-ddr", 1104 "cpu-ufs"; 1105 1106 power-domains = <&gcc UFS_PHY_GDSC>; 1107 1108 iommus = <&apps_smmu 0x300 0x0>; 1109 dma-coherent; 1110 1111 lanes-per-direction = <1>; 1112 1113 phys = <&ufs_mem_phy>; 1114 phy-names = "ufsphy"; 1115 1116 #reset-cells = <1>; 1117 1118 status = "disabled"; 1119 1120 ufs_opp_table: opp-table { 1121 compatible = "operating-points-v2"; 1122 1123 opp-50000000 { 1124 opp-hz = /bits/ 64 <50000000>, 1125 /bits/ 64 <0>, 1126 /bits/ 64 <0>, 1127 /bits/ 64 <37500000>, 1128 /bits/ 64 <0>, 1129 /bits/ 64 <0>, 1130 /bits/ 64 <0>, 1131 /bits/ 64 <75000000>; 1132 required-opps = <&rpmhpd_opp_low_svs>; 1133 }; 1134 1135 opp-100000000 { 1136 opp-hz = /bits/ 64 <100000000>, 1137 /bits/ 64 <0>, 1138 /bits/ 64 <0>, 1139 /bits/ 64 <75000000>, 1140 /bits/ 64 <0>, 1141 /bits/ 64 <0>, 1142 /bits/ 64 <0>, 1143 /bits/ 64 <150000000>; 1144 required-opps = <&rpmhpd_opp_svs>; 1145 }; 1146 1147 opp-200000000 { 1148 opp-hz = /bits/ 64 <200000000>, 1149 /bits/ 64 <0>, 1150 /bits/ 64 <0>, 1151 /bits/ 64 <150000000>, 1152 /bits/ 64 <0>, 1153 /bits/ 64 <0>, 1154 /bits/ 64 <0>, 1155 /bits/ 64 <300000000>; 1156 required-opps = <&rpmhpd_opp_nom>; 1157 }; 1158 }; 1159 }; 1160 1161 ufs_mem_phy: phy@1d87000 { 1162 compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy"; 1163 reg = <0x0 0x01d87000 0x0 0xe00>; 1164 clocks = <&rpmhcc RPMH_CXO_CLK>, 1165 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1166 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1167 clock-names = "ref", 1168 "ref_aux", 1169 "qref"; 1170 1171 power-domains = <&gcc UFS_PHY_GDSC>; 1172 1173 resets = <&ufs_mem_hc 0>; 1174 reset-names = "ufsphy"; 1175 1176 #clock-cells = <1>; 1177 #phy-cells = <0>; 1178 1179 status = "disabled"; 1180 }; 1181 1182 cryptobam: dma-controller@1dc4000 { 1183 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1184 reg = <0x0 0x01dc4000 0x0 0x24000>; 1185 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1186 #dma-cells = <1>; 1187 qcom,ee = <0>; 1188 qcom,controlled-remotely; 1189 num-channels = <16>; 1190 qcom,num-ees = <4>; 1191 iommus = <&apps_smmu 0x0104 0x0011>; 1192 }; 1193 1194 crypto: crypto@1dfa000 { 1195 compatible = "qcom,qcs615-qce", "qcom,sm8150-qce", "qcom,qce"; 1196 reg = <0x0 0x01dfa000 0x0 0x6000>; 1197 dmas = <&cryptobam 4>, <&cryptobam 5>; 1198 dma-names = "rx", "tx"; 1199 iommus = <&apps_smmu 0x0104 0x0011>; 1200 interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 1201 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1202 interconnect-names = "memory"; 1203 }; 1204 1205 tcsr_mutex: hwlock@1f40000 { 1206 compatible = "qcom,tcsr-mutex"; 1207 reg = <0x0 0x01f40000 0x0 0x20000>; 1208 #hwlock-cells = <1>; 1209 }; 1210 1211 tcsr: syscon@1fc0000 { 1212 compatible = "qcom,qcs615-tcsr", "syscon"; 1213 reg = <0x0 0x01fc0000 0x0 0x30000>; 1214 }; 1215 1216 tlmm: pinctrl@3100000 { 1217 compatible = "qcom,qcs615-tlmm"; 1218 reg = <0x0 0x03100000 0x0 0x300000>, 1219 <0x0 0x03500000 0x0 0x300000>, 1220 <0x0 0x03d00000 0x0 0x300000>; 1221 reg-names = "east", 1222 "west", 1223 "south"; 1224 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1225 gpio-ranges = <&tlmm 0 0 124>; 1226 gpio-controller; 1227 #gpio-cells = <2>; 1228 interrupt-controller; 1229 #interrupt-cells = <2>; 1230 wakeup-parent = <&pdc>; 1231 1232 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 1233 pins = "gpio4", "gpio5"; 1234 function = "qup0"; 1235 1236 }; 1237 1238 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 1239 pins = "gpio0", "gpio1"; 1240 function = "qup0"; 1241 }; 1242 1243 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 1244 pins = "gpio18", "gpio19"; 1245 function = "qup0"; 1246 }; 1247 1248 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 1249 pins = "gpio20", "gpio21"; 1250 function = "qup1"; 1251 }; 1252 1253 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 1254 pins = "gpio14", "gpio15"; 1255 function = "qup1"; 1256 }; 1257 1258 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 1259 pins = "gpio6", "gpio7"; 1260 function = "qup1"; 1261 }; 1262 1263 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 1264 pins = "gpio10", "gpio11"; 1265 function = "qup1"; 1266 }; 1267 1268 qup_spi2_data_clk: qup-spi2-data-clk-state { 1269 pins = "gpio0", "gpio1", "gpio2"; 1270 function = "qup0"; 1271 }; 1272 1273 qup_spi2_cs: qup-spi2-cs-state { 1274 pins = "gpio3"; 1275 function = "qup0"; 1276 }; 1277 1278 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 1279 pins = "gpio3"; 1280 function = "gpio"; 1281 }; 1282 1283 qup_spi4_data_clk: qup-spi4-data-clk-state { 1284 pins = "gpio20", "gpio21", "gpio22"; 1285 function = "qup1"; 1286 }; 1287 1288 qup_spi4_cs: qup-spi4-cs-state { 1289 pins = "gpio23"; 1290 function = "qup1"; 1291 }; 1292 1293 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 1294 pins = "gpio23"; 1295 function = "gpio"; 1296 }; 1297 1298 qup_spi6_data_clk: qup-spi6-data-clk-state { 1299 pins = "gpio6", "gpio7", "gpio8"; 1300 function = "qup1"; 1301 }; 1302 1303 qup_spi6_cs: qup-spi6-cs-state { 1304 pins = "gpio9"; 1305 function = "qup1"; 1306 }; 1307 1308 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1309 pins = "gpio9"; 1310 function = "gpio"; 1311 }; 1312 1313 qup_spi7_data_clk: qup-spi7-data-clk-state { 1314 pins = "gpio10", "gpio11", "gpio12"; 1315 function = "qup1"; 1316 }; 1317 1318 qup_spi7_cs: qup-spi7-cs-state { 1319 pins = "gpio13"; 1320 function = "qup1"; 1321 }; 1322 1323 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 1324 pins = "gpio13"; 1325 function = "gpio"; 1326 }; 1327 1328 qup_uart0_tx: qup-uart0-tx-state { 1329 pins = "gpio16"; 1330 function = "qup0"; 1331 }; 1332 1333 qup_uart0_rx: qup-uart0-rx-state { 1334 pins = "gpio17"; 1335 function = "qup0"; 1336 }; 1337 1338 qup_uart2_cts: qup-uart2-cts-state { 1339 pins = "gpio0"; 1340 function = "qup0"; 1341 }; 1342 1343 qup_uart2_rts: qup-uart2-rts-state { 1344 pins = "gpio1"; 1345 function = "qup0"; 1346 }; 1347 1348 qup_uart2_tx: qup-uart2-tx-state { 1349 pins = "gpio2"; 1350 function = "qup0"; 1351 }; 1352 1353 qup_uart2_rx: qup-uart2-rx-state { 1354 pins = "gpio3"; 1355 function = "qup0"; 1356 }; 1357 1358 qup_uart4_cts: qup-uart4-cts-state { 1359 pins = "gpio20"; 1360 function = "qup1"; 1361 }; 1362 1363 qup_uart4_rts: qup-uart4-rts-state { 1364 pins = "gpio21"; 1365 function = "qup1"; 1366 }; 1367 1368 qup_uart4_tx: qup-uart4-tx-state { 1369 pins = "gpio22"; 1370 function = "qup1"; 1371 }; 1372 1373 qup_uart4_rx: qup-uart4-rx-state { 1374 pins = "gpio23"; 1375 function = "qup1"; 1376 }; 1377 1378 qup_uart6_cts: qup-uart6-cts-state { 1379 pins = "gpio6"; 1380 function = "qup1"; 1381 }; 1382 1383 qup_uart6_rts: qup-uart6-rts-state { 1384 pins = "gpio7"; 1385 function = "qup1"; 1386 }; 1387 1388 qup_uart6_tx: qup-uart6-tx-state { 1389 pins = "gpio8"; 1390 function = "qup1"; 1391 }; 1392 1393 qup_uart6_rx: qup-uart6-rx-state { 1394 pins = "gpio9"; 1395 function = "qup1"; 1396 }; 1397 1398 qup_uart7_cts: qup-uart7-cts-state { 1399 pins = "gpio10"; 1400 function = "qup1"; 1401 }; 1402 1403 qup_uart7_rts: qup-uart7-rts-state { 1404 pins = "gpio11"; 1405 function = "qup1"; 1406 }; 1407 1408 qup_uart7_tx: qup-uart7-tx-state { 1409 pins = "gpio12"; 1410 function = "qup1"; 1411 }; 1412 1413 qup_uart7_rx: qup-uart7-rx-state { 1414 pins = "gpio13"; 1415 function = "qup1"; 1416 }; 1417 1418 sdc1_state_on: sdc1-on-state { 1419 clk-pins { 1420 pins = "sdc1_clk"; 1421 bias-disable; 1422 drive-strength = <16>; 1423 }; 1424 1425 cmd-pins { 1426 pins = "sdc1_cmd"; 1427 bias-pull-up; 1428 drive-strength = <10>; 1429 }; 1430 1431 data-pins { 1432 pins = "sdc1_data"; 1433 bias-pull-up; 1434 drive-strength = <10>; 1435 }; 1436 1437 rclk-pins { 1438 pins = "sdc1_rclk"; 1439 bias-pull-down; 1440 }; 1441 }; 1442 1443 sdc1_state_off: sdc1-off-state { 1444 clk-pins { 1445 pins = "sdc1_clk"; 1446 bias-disable; 1447 drive-strength = <2>; 1448 }; 1449 1450 cmd-pins { 1451 pins = "sdc1_cmd"; 1452 bias-pull-up; 1453 drive-strength = <2>; 1454 }; 1455 1456 data-pins { 1457 pins = "sdc1_data"; 1458 bias-pull-up; 1459 drive-strength = <2>; 1460 }; 1461 1462 rclk-pins { 1463 pins = "sdc1_rclk"; 1464 bias-pull-down; 1465 }; 1466 }; 1467 1468 sdc2_state_on: sdc2-on-state { 1469 clk-pins { 1470 pins = "sdc2_clk"; 1471 bias-disable; 1472 drive-strength = <16>; 1473 }; 1474 1475 cmd-pins { 1476 pins = "sdc2_cmd"; 1477 bias-pull-up; 1478 drive-strength = <10>; 1479 }; 1480 1481 data-pins { 1482 pins = "sdc2_data"; 1483 bias-pull-up; 1484 drive-strength = <10>; 1485 }; 1486 }; 1487 1488 sdc2_state_off: sdc2-off-state { 1489 clk-pins { 1490 pins = "sdc2_clk"; 1491 bias-disable; 1492 drive-strength = <2>; 1493 }; 1494 1495 cmd-pins { 1496 pins = "sdc2_cmd"; 1497 bias-pull-up; 1498 drive-strength = <2>; 1499 }; 1500 1501 data-pins { 1502 pins = "sdc2_data"; 1503 bias-pull-up; 1504 drive-strength = <2>; 1505 }; 1506 }; 1507 }; 1508 1509 stm@6002000 { 1510 compatible = "arm,coresight-stm", "arm,primecell"; 1511 reg = <0x0 0x06002000 0x0 0x1000>, 1512 <0x0 0x16280000 0x0 0x180000>; 1513 reg-names = "stm-base", 1514 "stm-stimulus-base"; 1515 1516 clocks = <&aoss_qmp>; 1517 clock-names = "apb_pclk"; 1518 1519 out-ports { 1520 port { 1521 stm_out: endpoint { 1522 remote-endpoint = <&funnel_in0_in7>; 1523 }; 1524 }; 1525 }; 1526 }; 1527 1528 tpda@6004000 { 1529 compatible = "qcom,coresight-tpda", "arm,primecell"; 1530 reg = <0x0 0x06004000 0x0 0x1000>; 1531 1532 clocks = <&aoss_qmp>; 1533 clock-names = "apb_pclk"; 1534 1535 in-ports { 1536 #address-cells = <1>; 1537 #size-cells = <0>; 1538 1539 port@0 { 1540 reg = <0>; 1541 1542 tpda_qdss_in0: endpoint { 1543 remote-endpoint = <&tpdm_center_out>; 1544 }; 1545 }; 1546 1547 port@4 { 1548 reg = <4>; 1549 1550 tpda_qdss_in4: endpoint { 1551 remote-endpoint = <&funnel_monaq_out>; 1552 }; 1553 }; 1554 1555 port@5 { 1556 reg = <5>; 1557 1558 tpda_qdss_in5: endpoint { 1559 remote-endpoint = <&funnel_ddr_0_out>; 1560 }; 1561 }; 1562 1563 port@6 { 1564 reg = <6>; 1565 1566 tpda_qdss_in6: endpoint { 1567 remote-endpoint = <&funnel_turing_out>; 1568 }; 1569 }; 1570 1571 port@7 { 1572 reg = <7>; 1573 1574 tpda_qdss_in7: endpoint { 1575 remote-endpoint = <&tpdm_vsense_out>; 1576 }; 1577 }; 1578 1579 port@8 { 1580 reg = <8>; 1581 1582 tpda_qdss_in8: endpoint { 1583 remote-endpoint = <&tpdm_dcc_out>; 1584 }; 1585 }; 1586 1587 port@9 { 1588 reg = <9>; 1589 1590 tpda_qdss_in9: endpoint { 1591 remote-endpoint = <&tpdm_prng_out>; 1592 }; 1593 }; 1594 1595 port@b { 1596 reg = <11>; 1597 1598 tpda_qdss_in11: endpoint { 1599 remote-endpoint = <&tpdm_qm_out>; 1600 }; 1601 }; 1602 1603 port@c { 1604 reg = <12>; 1605 1606 tpda_qdss_in12: endpoint { 1607 remote-endpoint = <&tpdm_west_out>; 1608 }; 1609 }; 1610 1611 port@d { 1612 reg = <13>; 1613 1614 tpda_qdss_in13: endpoint { 1615 remote-endpoint = <&tpdm_pimem_out>; 1616 }; 1617 }; 1618 }; 1619 1620 out-ports { 1621 port { 1622 tpda_qdss_out: endpoint { 1623 remote-endpoint = <&funnel_qatb_in>; 1624 }; 1625 }; 1626 }; 1627 }; 1628 1629 funnel@6005000 { 1630 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1631 reg = <0x0 0x06005000 0x0 0x1000>; 1632 1633 clocks = <&aoss_qmp>; 1634 clock-names = "apb_pclk"; 1635 1636 in-ports { 1637 port { 1638 funnel_qatb_in: endpoint { 1639 remote-endpoint = <&tpda_qdss_out>; 1640 }; 1641 }; 1642 }; 1643 1644 out-ports { 1645 port { 1646 funnel_qatb_out: endpoint { 1647 remote-endpoint = <&funnel_in0_in6>; 1648 }; 1649 }; 1650 }; 1651 }; 1652 1653 cti@6010000 { 1654 compatible = "arm,coresight-cti", "arm,primecell"; 1655 reg = <0x0 0x06010000 0x0 0x1000>; 1656 1657 clocks = <&aoss_qmp>; 1658 clock-names = "apb_pclk"; 1659 }; 1660 1661 cti@6011000 { 1662 compatible = "arm,coresight-cti", "arm,primecell"; 1663 reg = <0x0 0x06011000 0x0 0x1000>; 1664 1665 clocks = <&aoss_qmp>; 1666 clock-names = "apb_pclk"; 1667 }; 1668 1669 cti@6012000 { 1670 compatible = "arm,coresight-cti", "arm,primecell"; 1671 reg = <0x0 0x06012000 0x0 0x1000>; 1672 1673 clocks = <&aoss_qmp>; 1674 clock-names = "apb_pclk"; 1675 }; 1676 1677 cti@6013000 { 1678 compatible = "arm,coresight-cti", "arm,primecell"; 1679 reg = <0x0 0x06013000 0x0 0x1000>; 1680 1681 clocks = <&aoss_qmp>; 1682 clock-names = "apb_pclk"; 1683 }; 1684 1685 cti@6014000 { 1686 compatible = "arm,coresight-cti", "arm,primecell"; 1687 reg = <0x0 0x06014000 0x0 0x1000>; 1688 1689 clocks = <&aoss_qmp>; 1690 clock-names = "apb_pclk"; 1691 }; 1692 1693 cti@6015000 { 1694 compatible = "arm,coresight-cti", "arm,primecell"; 1695 reg = <0x0 0x06015000 0x0 0x1000>; 1696 1697 clocks = <&aoss_qmp>; 1698 clock-names = "apb_pclk"; 1699 }; 1700 1701 cti@6016000 { 1702 compatible = "arm,coresight-cti", "arm,primecell"; 1703 reg = <0x0 0x06016000 0x0 0x1000>; 1704 1705 clocks = <&aoss_qmp>; 1706 clock-names = "apb_pclk"; 1707 }; 1708 1709 cti@6017000 { 1710 compatible = "arm,coresight-cti", "arm,primecell"; 1711 reg = <0x0 0x06017000 0x0 0x1000>; 1712 1713 clocks = <&aoss_qmp>; 1714 clock-names = "apb_pclk"; 1715 }; 1716 1717 cti@6018000 { 1718 compatible = "arm,coresight-cti", "arm,primecell"; 1719 reg = <0x0 0x06018000 0x0 0x1000>; 1720 1721 clocks = <&aoss_qmp>; 1722 clock-names = "apb_pclk"; 1723 }; 1724 1725 cti@6019000 { 1726 compatible = "arm,coresight-cti", "arm,primecell"; 1727 reg = <0x0 0x06019000 0x0 0x1000>; 1728 1729 clocks = <&aoss_qmp>; 1730 clock-names = "apb_pclk"; 1731 }; 1732 1733 cti@601a000 { 1734 compatible = "arm,coresight-cti", "arm,primecell"; 1735 reg = <0x0 0x0601a000 0x0 0x1000>; 1736 1737 clocks = <&aoss_qmp>; 1738 clock-names = "apb_pclk"; 1739 }; 1740 1741 cti@601b000 { 1742 compatible = "arm,coresight-cti", "arm,primecell"; 1743 reg = <0x0 0x0601b000 0x0 0x1000>; 1744 1745 clocks = <&aoss_qmp>; 1746 clock-names = "apb_pclk"; 1747 }; 1748 1749 cti@601c000 { 1750 compatible = "arm,coresight-cti", "arm,primecell"; 1751 reg = <0x0 0x0601c000 0x0 0x1000>; 1752 1753 clocks = <&aoss_qmp>; 1754 clock-names = "apb_pclk"; 1755 }; 1756 1757 cti@601d000 { 1758 compatible = "arm,coresight-cti", "arm,primecell"; 1759 reg = <0x0 0x0601d000 0x0 0x1000>; 1760 1761 clocks = <&aoss_qmp>; 1762 clock-names = "apb_pclk"; 1763 }; 1764 1765 cti@601e000 { 1766 compatible = "arm,coresight-cti", "arm,primecell"; 1767 reg = <0x0 0x0601e000 0x0 0x1000>; 1768 1769 clocks = <&aoss_qmp>; 1770 clock-names = "apb_pclk"; 1771 }; 1772 1773 cti@601f000 { 1774 compatible = "arm,coresight-cti", "arm,primecell"; 1775 reg = <0x0 0x0601f000 0x0 0x1000>; 1776 1777 clocks = <&aoss_qmp>; 1778 clock-names = "apb_pclk"; 1779 }; 1780 1781 funnel@6041000 { 1782 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1783 reg = <0x0 0x06041000 0x0 0x1000>; 1784 1785 clocks = <&aoss_qmp>; 1786 clock-names = "apb_pclk"; 1787 1788 in-ports { 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 1792 port@6 { 1793 reg = <6>; 1794 1795 funnel_in0_in6: endpoint { 1796 remote-endpoint = <&funnel_qatb_out>; 1797 }; 1798 }; 1799 1800 port@7 { 1801 reg = <7>; 1802 1803 funnel_in0_in7: endpoint { 1804 remote-endpoint = <&stm_out>; 1805 }; 1806 }; 1807 }; 1808 1809 out-ports { 1810 port { 1811 funnel_in0_out: endpoint { 1812 remote-endpoint = <&funnel_merg_in0>; 1813 }; 1814 }; 1815 }; 1816 }; 1817 1818 funnel@6042000 { 1819 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1820 reg = <0x0 0x06042000 0x0 0x1000>; 1821 1822 clocks = <&aoss_qmp>; 1823 clock-names = "apb_pclk"; 1824 1825 in-ports { 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 1829 port@3 { 1830 reg = <3>; 1831 1832 funnel_in1_in3: endpoint { 1833 remote-endpoint = <&replicator_swao_out0>; 1834 }; 1835 }; 1836 1837 port@4 { 1838 reg = <4>; 1839 1840 funnel_in1_in4: endpoint { 1841 remote-endpoint = <&tpdm_wcss_out>; 1842 }; 1843 }; 1844 1845 port@7 { 1846 reg = <7>; 1847 1848 funnel_in1_in7: endpoint { 1849 remote-endpoint = <&funnel_apss_merg_out>; 1850 }; 1851 }; 1852 }; 1853 1854 out-ports { 1855 port { 1856 funnel_in1_out: endpoint { 1857 remote-endpoint = <&funnel_merg_in1>; 1858 }; 1859 }; 1860 }; 1861 }; 1862 1863 funnel@6045000 { 1864 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1865 reg = <0x0 0x06045000 0x0 0x1000>; 1866 1867 clocks = <&aoss_qmp>; 1868 clock-names = "apb_pclk"; 1869 1870 in-ports { 1871 #address-cells = <1>; 1872 #size-cells = <0>; 1873 1874 port@0 { 1875 reg = <0>; 1876 1877 funnel_merg_in0: endpoint { 1878 remote-endpoint = <&funnel_in0_out>; 1879 }; 1880 }; 1881 1882 port@1 { 1883 reg = <1>; 1884 1885 funnel_merg_in1: endpoint { 1886 remote-endpoint = <&funnel_in1_out>; 1887 }; 1888 }; 1889 }; 1890 1891 out-ports { 1892 port { 1893 funnel_merg_out: endpoint { 1894 remote-endpoint = <&tmc_etf_in>; 1895 }; 1896 }; 1897 }; 1898 }; 1899 1900 replicator@6046000 { 1901 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1902 reg = <0x0 0x06046000 0x0 0x1000>; 1903 1904 clocks = <&aoss_qmp>; 1905 clock-names = "apb_pclk"; 1906 1907 in-ports { 1908 port { 1909 replicator0_in: endpoint { 1910 remote-endpoint = <&tmc_etf_out>; 1911 }; 1912 }; 1913 }; 1914 1915 out-ports { 1916 #address-cells = <1>; 1917 #size-cells = <0>; 1918 1919 port@1 { 1920 reg = <1>; 1921 1922 replicator0_out1: endpoint { 1923 remote-endpoint = <&replicator1_in>; 1924 }; 1925 }; 1926 }; 1927 }; 1928 1929 tmc@6047000 { 1930 compatible = "arm,coresight-tmc", "arm,primecell"; 1931 reg = <0x0 0x06047000 0x0 0x1000>; 1932 1933 clocks = <&aoss_qmp>; 1934 clock-names = "apb_pclk"; 1935 1936 in-ports { 1937 port { 1938 tmc_etf_in: endpoint { 1939 remote-endpoint = <&funnel_merg_out>; 1940 }; 1941 }; 1942 }; 1943 1944 out-ports { 1945 port { 1946 tmc_etf_out: endpoint { 1947 remote-endpoint = <&replicator0_in>; 1948 }; 1949 }; 1950 }; 1951 }; 1952 1953 replicator@604a000 { 1954 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1955 reg = <0x0 0x0604a000 0x0 0x1000>; 1956 1957 clocks = <&aoss_qmp>; 1958 clock-names = "apb_pclk"; 1959 status = "disabled"; 1960 1961 in-ports { 1962 port { 1963 replicator1_in: endpoint { 1964 remote-endpoint = <&replicator0_out1>; 1965 }; 1966 }; 1967 }; 1968 1969 out-ports { 1970 port { 1971 replicator1_out: endpoint { 1972 remote-endpoint = <&funnel_swao_in6>; 1973 }; 1974 }; 1975 }; 1976 }; 1977 1978 cti@683b000 { 1979 compatible = "arm,coresight-cti", "arm,primecell"; 1980 reg = <0x0 0x0683b000 0x0 0x1000>; 1981 1982 clocks = <&aoss_qmp>; 1983 clock-names = "apb_pclk"; 1984 }; 1985 1986 tpdm@6840000 { 1987 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1988 reg = <0x0 0x06840000 0x0 0x1000>; 1989 1990 clocks = <&aoss_qmp>; 1991 clock-names = "apb_pclk"; 1992 1993 qcom,cmb-element-bits = <64>; 1994 qcom,cmb-msrs-num = <32>; 1995 status = "disabled"; 1996 1997 out-ports { 1998 port { 1999 tpdm_vsense_out: endpoint { 2000 remote-endpoint = <&tpda_qdss_in7>; 2001 }; 2002 }; 2003 }; 2004 }; 2005 2006 tpdm@684c000 { 2007 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2008 reg = <0x0 0x0684c000 0x0 0x1000>; 2009 2010 clocks = <&aoss_qmp>; 2011 clock-names = "apb_pclk"; 2012 2013 qcom,cmb-element-bits = <32>; 2014 qcom,cmb-msrs-num = <32>; 2015 2016 out-ports { 2017 port { 2018 tpdm_prng_out: endpoint { 2019 remote-endpoint = <&tpda_qdss_in9>; 2020 }; 2021 }; 2022 }; 2023 }; 2024 2025 tpdm@6850000 { 2026 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2027 reg = <0x0 0x06850000 0x0 0x1000>; 2028 2029 clocks = <&aoss_qmp>; 2030 clock-names = "apb_pclk"; 2031 2032 qcom,cmb-element-bits = <64>; 2033 qcom,cmb-msrs-num = <32>; 2034 qcom,dsb-element-bits = <32>; 2035 qcom,dsb-msrs-num = <32>; 2036 2037 out-ports { 2038 port { 2039 tpdm_pimem_out: endpoint { 2040 remote-endpoint = <&tpda_qdss_in13>; 2041 }; 2042 }; 2043 }; 2044 }; 2045 2046 tpdm@6860000 { 2047 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2048 reg = <0x0 0x06860000 0x0 0x1000>; 2049 2050 clocks = <&aoss_qmp>; 2051 clock-names = "apb_pclk"; 2052 2053 qcom,dsb-element-bits = <32>; 2054 qcom,dsb-msrs-num = <32>; 2055 2056 out-ports { 2057 port { 2058 tpdm_turing_out: endpoint { 2059 remote-endpoint = <&funnel_turing_in>; 2060 }; 2061 }; 2062 }; 2063 }; 2064 2065 funnel@6861000 { 2066 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2067 reg = <0x0 0x06861000 0x0 0x1000>; 2068 2069 clocks = <&aoss_qmp>; 2070 clock-names = "apb_pclk"; 2071 2072 in-ports { 2073 port { 2074 funnel_turing_in: endpoint { 2075 remote-endpoint = <&tpdm_turing_out>; 2076 }; 2077 }; 2078 }; 2079 2080 out-ports { 2081 port { 2082 funnel_turing_out: endpoint { 2083 remote-endpoint = <&tpda_qdss_in6>; 2084 }; 2085 }; 2086 }; 2087 }; 2088 2089 cti@6867000 { 2090 compatible = "arm,coresight-cti", "arm,primecell"; 2091 reg = <0x0 0x06867000 0x0 0x1000>; 2092 2093 clocks = <&aoss_qmp>; 2094 clock-names = "apb_pclk"; 2095 }; 2096 2097 tpdm@6870000 { 2098 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2099 reg = <0x0 0x06870000 0x0 0x1000>; 2100 2101 clocks = <&aoss_qmp>; 2102 clock-names = "apb_pclk"; 2103 2104 qcom,cmb-element-bits = <32>; 2105 qcom,cmb-msrs-num = <32>; 2106 status = "disabled"; 2107 2108 out-ports { 2109 port { 2110 tpdm_dcc_out: endpoint { 2111 remote-endpoint = <&tpda_qdss_in8>; 2112 }; 2113 }; 2114 }; 2115 }; 2116 2117 tpdm@699c000 { 2118 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2119 reg = <0x0 0x0699c000 0x0 0x1000>; 2120 2121 clocks = <&aoss_qmp>; 2122 clock-names = "apb_pclk"; 2123 2124 qcom,cmb-element-bits = <32>; 2125 qcom,cmb-msrs-num = <32>; 2126 qcom,dsb-element-bits = <32>; 2127 qcom,dsb-msrs-num = <32>; 2128 status = "disabled"; 2129 2130 out-ports { 2131 port { 2132 tpdm_wcss_out: endpoint { 2133 remote-endpoint = <&funnel_in1_in4>; 2134 }; 2135 }; 2136 }; 2137 }; 2138 2139 tpdm@69c0000 { 2140 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2141 reg = <0x0 0x069c0000 0x0 0x1000>; 2142 2143 clocks = <&aoss_qmp>; 2144 clock-names = "apb_pclk"; 2145 2146 qcom,dsb-element-bits = <32>; 2147 qcom,dsb-msrs-num = <32>; 2148 2149 out-ports { 2150 port { 2151 tpdm_monaq_out: endpoint { 2152 remote-endpoint = <&funnel_monaq_in>; 2153 }; 2154 }; 2155 }; 2156 }; 2157 2158 funnel@69c3000 { 2159 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2160 reg = <0x0 0x069c3000 0x0 0x1000>; 2161 2162 clocks = <&aoss_qmp>; 2163 clock-names = "apb_pclk"; 2164 2165 in-ports { 2166 port { 2167 funnel_monaq_in: endpoint { 2168 remote-endpoint = <&tpdm_monaq_out>; 2169 }; 2170 }; 2171 }; 2172 2173 out-ports { 2174 port { 2175 funnel_monaq_out: endpoint { 2176 remote-endpoint = <&tpda_qdss_in4>; 2177 }; 2178 }; 2179 }; 2180 }; 2181 2182 tpdm@69d0000 { 2183 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2184 reg = <0x0 0x069d0000 0x0 0x1000>; 2185 2186 clocks = <&aoss_qmp>; 2187 clock-names = "apb_pclk"; 2188 2189 qcom,dsb-element-bits = <32>; 2190 qcom,dsb-msrs-num = <32>; 2191 status = "disabled"; 2192 2193 out-ports { 2194 port { 2195 tpdm_qm_out: endpoint { 2196 remote-endpoint = <&tpda_qdss_in11>; 2197 }; 2198 }; 2199 }; 2200 }; 2201 2202 tpdm@6a00000 { 2203 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2204 reg = <0x0 0x06a00000 0x0 0x1000>; 2205 2206 clocks = <&aoss_qmp>; 2207 clock-names = "apb_pclk"; 2208 2209 qcom,dsb-element-bits = <32>; 2210 qcom,dsb-msrs-num = <32>; 2211 status = "disabled"; 2212 2213 out-ports { 2214 port { 2215 tpdm_ddr_out: endpoint { 2216 remote-endpoint = <&funnel_ddr_0_in>; 2217 }; 2218 }; 2219 }; 2220 }; 2221 2222 cti@6a02000 { 2223 compatible = "arm,coresight-cti", "arm,primecell"; 2224 reg = <0x0 0x06a02000 0x0 0x1000>; 2225 2226 clocks = <&aoss_qmp>; 2227 clock-names = "apb_pclk"; 2228 }; 2229 2230 cti@6a03000 { 2231 compatible = "arm,coresight-cti", "arm,primecell"; 2232 reg = <0x0 0x06a03000 0x0 0x1000>; 2233 2234 clocks = <&aoss_qmp>; 2235 clock-names = "apb_pclk"; 2236 }; 2237 2238 cti@6a10000 { 2239 compatible = "arm,coresight-cti", "arm,primecell"; 2240 reg = <0x0 0x06a10000 0x0 0x1000>; 2241 2242 clocks = <&aoss_qmp>; 2243 clock-names = "apb_pclk"; 2244 }; 2245 2246 cti@6a11000 { 2247 compatible = "arm,coresight-cti", "arm,primecell"; 2248 reg = <0x0 0x06a11000 0x0 0x1000>; 2249 2250 clocks = <&aoss_qmp>; 2251 clock-names = "apb_pclk"; 2252 }; 2253 2254 funnel@6a05000 { 2255 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2256 reg = <0x0 0x06a05000 0x0 0x1000>; 2257 2258 clocks = <&aoss_qmp>; 2259 clock-names = "apb_pclk"; 2260 2261 in-ports { 2262 port { 2263 funnel_ddr_0_in: endpoint { 2264 remote-endpoint = <&tpdm_ddr_out>; 2265 }; 2266 }; 2267 }; 2268 2269 out-ports { 2270 port { 2271 funnel_ddr_0_out: endpoint { 2272 remote-endpoint = <&tpda_qdss_in5>; 2273 }; 2274 }; 2275 }; 2276 }; 2277 2278 tpda@6b01000 { 2279 compatible = "qcom,coresight-tpda", "arm,primecell"; 2280 reg = <0x0 0x06b01000 0x0 0x1000>; 2281 2282 clocks = <&aoss_qmp>; 2283 clock-names = "apb_pclk"; 2284 2285 in-ports { 2286 #address-cells = <1>; 2287 #size-cells = <0>; 2288 2289 port@0 { 2290 reg = <0>; 2291 2292 tpda_swao_in0: endpoint { 2293 remote-endpoint = <&tpdm_swao0_out>; 2294 }; 2295 }; 2296 2297 port@1 { 2298 reg = <1>; 2299 2300 tpda_swao_in1: endpoint { 2301 remote-endpoint = <&tpdm_swao1_out>; 2302 }; 2303 2304 }; 2305 }; 2306 2307 out-ports { 2308 port { 2309 tpda_swao_out: endpoint { 2310 remote-endpoint = <&funnel_swao_in7>; 2311 }; 2312 }; 2313 }; 2314 }; 2315 2316 tpdm@6b02000 { 2317 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2318 reg = <0x0 0x06b02000 0x0 0x1000>; 2319 2320 clocks = <&aoss_qmp>; 2321 clock-names = "apb_pclk"; 2322 2323 qcom,cmb-element-bits = <64>; 2324 qcom,cmb-msrs-num = <32>; 2325 status = "disabled"; 2326 2327 out-ports { 2328 port { 2329 tpdm_swao0_out: endpoint { 2330 remote-endpoint = <&tpda_swao_in0>; 2331 }; 2332 }; 2333 }; 2334 }; 2335 2336 tpdm@6b03000 { 2337 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2338 reg = <0x0 0x06b03000 0x0 0x1000>; 2339 2340 clocks = <&aoss_qmp>; 2341 clock-names = "apb_pclk"; 2342 2343 qcom,dsb-element-bits = <32>; 2344 qcom,dsb-msrs-num = <32>; 2345 status = "disabled"; 2346 2347 out-ports { 2348 port { 2349 tpdm_swao1_out: endpoint { 2350 remote-endpoint = <&tpda_swao_in1>; 2351 }; 2352 }; 2353 }; 2354 }; 2355 2356 cti@6b04000 { 2357 compatible = "arm,coresight-cti", "arm,primecell"; 2358 reg = <0x0 0x06b04000 0x0 0x1000>; 2359 2360 clocks = <&aoss_qmp>; 2361 clock-names = "apb_pclk"; 2362 }; 2363 2364 cti@6b05000 { 2365 compatible = "arm,coresight-cti", "arm,primecell"; 2366 reg = <0x0 0x06b05000 0x0 0x1000>; 2367 2368 clocks = <&aoss_qmp>; 2369 clock-names = "apb_pclk"; 2370 }; 2371 2372 cti@6b06000 { 2373 compatible = "arm,coresight-cti", "arm,primecell"; 2374 reg = <0x0 0x06b06000 0x0 0x1000>; 2375 2376 clocks = <&aoss_qmp>; 2377 clock-names = "apb_pclk"; 2378 }; 2379 2380 cti@6b07000 { 2381 compatible = "arm,coresight-cti", "arm,primecell"; 2382 reg = <0x0 0x06b07000 0x0 0x1000>; 2383 2384 clocks = <&aoss_qmp>; 2385 clock-names = "apb_pclk"; 2386 }; 2387 2388 funnel@6b08000 { 2389 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2390 reg = <0x0 0x06b08000 0x0 0x1000>; 2391 2392 clocks = <&aoss_qmp>; 2393 clock-names = "apb_pclk"; 2394 2395 in-ports { 2396 #address-cells = <1>; 2397 #size-cells = <0>; 2398 2399 port@6 { 2400 reg = <6>; 2401 2402 funnel_swao_in6: endpoint { 2403 remote-endpoint = <&replicator1_out>; 2404 }; 2405 }; 2406 2407 port@7 { 2408 reg = <7>; 2409 2410 funnel_swao_in7: endpoint { 2411 remote-endpoint = <&tpda_swao_out>; 2412 }; 2413 }; 2414 }; 2415 2416 out-ports { 2417 port { 2418 funnel_swao_out: endpoint { 2419 remote-endpoint = <&tmc_etf_swao_in>; 2420 }; 2421 }; 2422 }; 2423 }; 2424 2425 tmc@6b09000 { 2426 compatible = "arm,coresight-tmc", "arm,primecell"; 2427 reg = <0x0 0x06b09000 0x0 0x1000>; 2428 2429 clocks = <&aoss_qmp>; 2430 clock-names = "apb_pclk"; 2431 2432 in-ports { 2433 port { 2434 tmc_etf_swao_in: endpoint { 2435 remote-endpoint = <&funnel_swao_out>; 2436 }; 2437 }; 2438 }; 2439 2440 out-ports { 2441 port { 2442 tmc_etf_swao_out: endpoint { 2443 remote-endpoint = <&replicator_swao_in>; 2444 }; 2445 }; 2446 }; 2447 }; 2448 2449 replicator@6b0a000 { 2450 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2451 reg = <0x0 0x06b0a000 0x0 0x1000>; 2452 2453 clocks = <&aoss_qmp>; 2454 clock-names = "apb_pclk"; 2455 2456 in-ports { 2457 port { 2458 replicator_swao_in: endpoint { 2459 remote-endpoint = <&tmc_etf_swao_out>; 2460 }; 2461 }; 2462 }; 2463 2464 out-ports { 2465 #address-cells = <1>; 2466 #size-cells = <0>; 2467 2468 port@0 { 2469 reg = <0>; 2470 2471 replicator_swao_out0: endpoint { 2472 remote-endpoint = <&funnel_in1_in3>; 2473 }; 2474 }; 2475 2476 port@1 { 2477 reg = <1>; 2478 2479 replicator_swao_out1: endpoint { 2480 remote-endpoint = <&eud_in>; 2481 }; 2482 }; 2483 }; 2484 }; 2485 2486 cti@6b21000 { 2487 compatible = "arm,coresight-cti", "arm,primecell"; 2488 reg = <0x0 0x06b21000 0x0 0x1000>; 2489 2490 clocks = <&aoss_qmp>; 2491 clock-names = "apb_pclk"; 2492 }; 2493 2494 tpdm@6b48000 { 2495 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2496 reg = <0x0 0x06b48000 0x0 0x1000>; 2497 2498 clocks = <&aoss_qmp>; 2499 clock-names = "apb_pclk"; 2500 2501 qcom,dsb-element-bits = <32>; 2502 qcom,dsb-msrs-num = <32>; 2503 2504 out-ports { 2505 port { 2506 tpdm_west_out: endpoint { 2507 remote-endpoint = <&tpda_qdss_in12>; 2508 }; 2509 }; 2510 }; 2511 }; 2512 2513 cti@6c13000 { 2514 compatible = "arm,coresight-cti", "arm,primecell"; 2515 reg = <0x0 0x06c13000 0x0 0x1000>; 2516 2517 clocks = <&aoss_qmp>; 2518 clock-names = "apb_pclk"; 2519 2520 /* Not all required clocks can be enabled from the OS */ 2521 status = "fail"; 2522 }; 2523 2524 cti@6c20000 { 2525 compatible = "arm,coresight-cti", "arm,primecell"; 2526 reg = <0x0 0x06c20000 0x0 0x1000>; 2527 2528 clocks = <&aoss_qmp>; 2529 clock-names = "apb_pclk"; 2530 status = "disabled"; 2531 }; 2532 2533 tpdm@6c28000 { 2534 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2535 reg = <0x0 0x06c28000 0x0 0x1000>; 2536 2537 clocks = <&aoss_qmp>; 2538 clock-names = "apb_pclk"; 2539 2540 qcom,dsb-element-bits = <32>; 2541 qcom,dsb-msrs-num = <32>; 2542 2543 out-ports { 2544 port { 2545 tpdm_center_out: endpoint { 2546 remote-endpoint = <&tpda_qdss_in0>; 2547 }; 2548 }; 2549 }; 2550 }; 2551 2552 cti@6c29000 { 2553 compatible = "arm,coresight-cti", "arm,primecell"; 2554 reg = <0x0 0x06c29000 0x0 0x1000>; 2555 2556 clocks = <&aoss_qmp>; 2557 clock-names = "apb_pclk"; 2558 }; 2559 2560 cti@6c2a000 { 2561 compatible = "arm,coresight-cti", "arm,primecell"; 2562 reg = <0x0 0x06c2a000 0x0 0x1000>; 2563 2564 clocks = <&aoss_qmp>; 2565 clock-names = "apb_pclk"; 2566 }; 2567 2568 cti@7020000 { 2569 compatible = "arm,coresight-cti", "arm,primecell"; 2570 reg = <0x0 0x07020000 0x0 0x1000>; 2571 2572 clocks = <&aoss_qmp>; 2573 clock-names = "apb_pclk"; 2574 }; 2575 2576 etm@7040000 { 2577 compatible = "arm,primecell"; 2578 reg = <0x0 0x07040000 0x0 0x1000>; 2579 cpu = <&cpu0>; 2580 2581 clocks = <&aoss_qmp>; 2582 clock-names = "apb_pclk"; 2583 2584 arm,coresight-loses-context-with-cpu; 2585 qcom,skip-power-up; 2586 2587 out-ports { 2588 port { 2589 etm0_out: endpoint { 2590 remote-endpoint = <&funnel_apss_in0>; 2591 }; 2592 }; 2593 }; 2594 }; 2595 2596 cti@7120000 { 2597 compatible = "arm,coresight-cti", "arm,primecell"; 2598 reg = <0x0 0x07120000 0x0 0x1000>; 2599 2600 clocks = <&aoss_qmp>; 2601 clock-names = "apb_pclk"; 2602 }; 2603 2604 etm@7140000 { 2605 compatible = "arm,primecell"; 2606 reg = <0x0 0x07140000 0x0 0x1000>; 2607 cpu = <&cpu1>; 2608 2609 clocks = <&aoss_qmp>; 2610 clock-names = "apb_pclk"; 2611 2612 arm,coresight-loses-context-with-cpu; 2613 qcom,skip-power-up; 2614 2615 out-ports { 2616 port { 2617 etm1_out: endpoint { 2618 remote-endpoint = <&funnel_apss_in1>; 2619 }; 2620 }; 2621 }; 2622 }; 2623 2624 cti@7220000 { 2625 compatible = "arm,coresight-cti", "arm,primecell"; 2626 reg = <0x0 0x07220000 0x0 0x1000>; 2627 2628 clocks = <&aoss_qmp>; 2629 clock-names = "apb_pclk"; 2630 }; 2631 2632 etm@7240000 { 2633 compatible = "arm,primecell"; 2634 reg = <0x0 0x07240000 0x0 0x1000>; 2635 cpu = <&cpu2>; 2636 2637 clocks = <&aoss_qmp>; 2638 clock-names = "apb_pclk"; 2639 2640 arm,coresight-loses-context-with-cpu; 2641 qcom,skip-power-up; 2642 2643 out-ports { 2644 port { 2645 etm2_out: endpoint { 2646 remote-endpoint = <&funnel_apss_in2>; 2647 }; 2648 }; 2649 }; 2650 }; 2651 2652 cti@7320000 { 2653 compatible = "arm,coresight-cti", "arm,primecell"; 2654 reg = <0x0 0x07320000 0x0 0x1000>; 2655 2656 clocks = <&aoss_qmp>; 2657 clock-names = "apb_pclk"; 2658 }; 2659 2660 etm@7340000 { 2661 compatible = "arm,primecell"; 2662 reg = <0x0 0x07340000 0x0 0x1000>; 2663 cpu = <&cpu3>; 2664 2665 clocks = <&aoss_qmp>; 2666 clock-names = "apb_pclk"; 2667 2668 arm,coresight-loses-context-with-cpu; 2669 qcom,skip-power-up; 2670 2671 out-ports { 2672 port { 2673 etm3_out: endpoint { 2674 remote-endpoint = <&funnel_apss_in3>; 2675 }; 2676 }; 2677 }; 2678 }; 2679 2680 cti@7420000 { 2681 compatible = "arm,coresight-cti", "arm,primecell"; 2682 reg = <0x0 0x07420000 0x0 0x1000>; 2683 2684 clocks = <&aoss_qmp>; 2685 clock-names = "apb_pclk"; 2686 }; 2687 2688 etm@7440000 { 2689 compatible = "arm,primecell"; 2690 reg = <0x0 0x07440000 0x0 0x1000>; 2691 cpu = <&cpu4>; 2692 2693 clocks = <&aoss_qmp>; 2694 clock-names = "apb_pclk"; 2695 2696 arm,coresight-loses-context-with-cpu; 2697 qcom,skip-power-up; 2698 2699 out-ports { 2700 port { 2701 etm4_out: endpoint { 2702 remote-endpoint = <&funnel_apss_in4>; 2703 }; 2704 }; 2705 }; 2706 }; 2707 2708 cti@7520000 { 2709 compatible = "arm,coresight-cti", "arm,primecell"; 2710 reg = <0x0 0x07520000 0x0 0x1000>; 2711 2712 clocks = <&aoss_qmp>; 2713 clock-names = "apb_pclk"; 2714 }; 2715 2716 etm@7540000 { 2717 compatible = "arm,primecell"; 2718 reg = <0x0 0x07540000 0x0 0x1000>; 2719 cpu = <&cpu5>; 2720 2721 clocks = <&aoss_qmp>; 2722 clock-names = "apb_pclk"; 2723 2724 arm,coresight-loses-context-with-cpu; 2725 qcom,skip-power-up; 2726 2727 out-ports { 2728 port { 2729 etm5_out: endpoint { 2730 remote-endpoint = <&funnel_apss_in5>; 2731 }; 2732 }; 2733 }; 2734 }; 2735 2736 cti@7620000 { 2737 compatible = "arm,coresight-cti", "arm,primecell"; 2738 reg = <0x0 0x07620000 0x0 0x1000>; 2739 2740 clocks = <&aoss_qmp>; 2741 clock-names = "apb_pclk"; 2742 }; 2743 2744 etm@7640000 { 2745 compatible = "arm,primecell"; 2746 reg = <0x0 0x07640000 0x0 0x1000>; 2747 cpu = <&cpu6>; 2748 2749 clocks = <&aoss_qmp>; 2750 clock-names = "apb_pclk"; 2751 2752 arm,coresight-loses-context-with-cpu; 2753 qcom,skip-power-up; 2754 2755 out-ports { 2756 port { 2757 etm6_out: endpoint { 2758 remote-endpoint = <&funnel_apss_in6>; 2759 }; 2760 }; 2761 }; 2762 }; 2763 2764 cti@7720000 { 2765 compatible = "arm,coresight-cti", "arm,primecell"; 2766 reg = <0x0 0x07720000 0x0 0x1000>; 2767 2768 clocks = <&aoss_qmp>; 2769 clock-names = "apb_pclk"; 2770 }; 2771 2772 etm@7740000 { 2773 compatible = "arm,primecell"; 2774 reg = <0x0 0x07740000 0x0 0x1000>; 2775 cpu = <&cpu7>; 2776 2777 clocks = <&aoss_qmp>; 2778 clock-names = "apb_pclk"; 2779 2780 arm,coresight-loses-context-with-cpu; 2781 qcom,skip-power-up; 2782 2783 out-ports { 2784 port { 2785 etm7_out: endpoint { 2786 remote-endpoint = <&funnel_apss_in7>; 2787 }; 2788 }; 2789 }; 2790 }; 2791 2792 funnel@7800000 { 2793 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2794 reg = <0x0 0x07800000 0x0 0x1000>; 2795 2796 clocks = <&aoss_qmp>; 2797 clock-names = "apb_pclk"; 2798 2799 in-ports { 2800 #address-cells = <1>; 2801 #size-cells = <0>; 2802 2803 port@0 { 2804 reg = <0>; 2805 2806 funnel_apss_in0: endpoint { 2807 remote-endpoint = <&etm0_out>; 2808 }; 2809 }; 2810 2811 port@1 { 2812 reg = <1>; 2813 2814 funnel_apss_in1: endpoint { 2815 remote-endpoint = <&etm1_out>; 2816 }; 2817 }; 2818 2819 port@2 { 2820 reg = <2>; 2821 2822 funnel_apss_in2: endpoint { 2823 remote-endpoint = <&etm2_out>; 2824 }; 2825 }; 2826 2827 port@3 { 2828 reg = <3>; 2829 2830 funnel_apss_in3: endpoint { 2831 remote-endpoint = <&etm3_out>; 2832 }; 2833 }; 2834 2835 port@4 { 2836 reg = <4>; 2837 2838 funnel_apss_in4: endpoint { 2839 remote-endpoint = <&etm4_out>; 2840 }; 2841 }; 2842 2843 port@5 { 2844 reg = <5>; 2845 2846 funnel_apss_in5: endpoint { 2847 remote-endpoint = <&etm5_out>; 2848 }; 2849 }; 2850 2851 port@6 { 2852 reg = <6>; 2853 2854 funnel_apss_in6: endpoint { 2855 remote-endpoint = <&etm6_out>; 2856 }; 2857 }; 2858 2859 port@7 { 2860 reg = <7>; 2861 2862 funnel_apss_in7: endpoint { 2863 remote-endpoint = <&etm7_out>; 2864 }; 2865 }; 2866 }; 2867 2868 out-ports { 2869 port { 2870 funnel_apss_out: endpoint { 2871 remote-endpoint = <&funnel_apss_merg_in0>; 2872 }; 2873 }; 2874 }; 2875 }; 2876 2877 funnel@7810000 { 2878 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2879 reg = <0x0 0x07810000 0x0 0x1000>; 2880 2881 clocks = <&aoss_qmp>; 2882 clock-names = "apb_pclk"; 2883 2884 in-ports { 2885 #address-cells = <1>; 2886 #size-cells = <0>; 2887 2888 port@0 { 2889 reg = <0>; 2890 2891 funnel_apss_merg_in0: endpoint { 2892 remote-endpoint = <&funnel_apss_out>; 2893 }; 2894 }; 2895 2896 port@2 { 2897 reg = <2>; 2898 2899 funnel_apss_merg_in2: endpoint { 2900 remote-endpoint = <&tpda_olc_out>; 2901 }; 2902 }; 2903 2904 port@3 { 2905 reg = <3>; 2906 2907 funnel_apss_merg_in3: endpoint { 2908 remote-endpoint = <&tpda_llm_silver_out>; 2909 }; 2910 }; 2911 2912 port@4 { 2913 reg = <4>; 2914 2915 funnel_apss_merg_in4: endpoint { 2916 remote-endpoint = <&tpda_llm_gold_out>; 2917 }; 2918 }; 2919 2920 port@5 { 2921 reg = <5>; 2922 2923 funnel_apss_merg_in5: endpoint { 2924 remote-endpoint = <&tpda_apss_out>; 2925 }; 2926 }; 2927 }; 2928 2929 out-ports { 2930 port { 2931 funnel_apss_merg_out: endpoint { 2932 remote-endpoint = <&funnel_in1_in7>; 2933 }; 2934 }; 2935 }; 2936 }; 2937 2938 tpdm@7830000 { 2939 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2940 reg = <0x0 0x07830000 0x0 0x1000>; 2941 2942 clocks = <&aoss_qmp>; 2943 clock-names = "apb_pclk"; 2944 2945 qcom,cmb-element-bits = <64>; 2946 qcom,cmb-msrs-num = <32>; 2947 2948 out-ports { 2949 port { 2950 tpdm_olc_out: endpoint { 2951 remote-endpoint = <&tpda_olc_in>; 2952 }; 2953 }; 2954 }; 2955 }; 2956 2957 tpda@7832000 { 2958 compatible = "qcom,coresight-tpda", "arm,primecell"; 2959 reg = <0x0 0x07832000 0x0 0x1000>; 2960 2961 clocks = <&aoss_qmp>; 2962 clock-names = "apb_pclk"; 2963 2964 in-ports { 2965 port { 2966 tpda_olc_in: endpoint { 2967 remote-endpoint = <&tpdm_olc_out>; 2968 }; 2969 }; 2970 }; 2971 2972 out-ports { 2973 port { 2974 tpda_olc_out: endpoint { 2975 remote-endpoint = <&funnel_apss_merg_in2>; 2976 }; 2977 }; 2978 }; 2979 }; 2980 2981 tpdm@7860000 { 2982 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2983 reg = <0x0 0x07860000 0x0 0x1000>; 2984 2985 clocks = <&aoss_qmp>; 2986 clock-names = "apb_pclk"; 2987 2988 qcom,dsb-element-bits = <32>; 2989 qcom,dsb-msrs-num = <32>; 2990 2991 out-ports { 2992 port { 2993 tpdm_apss_out: endpoint { 2994 remote-endpoint = <&tpda_apss_in>; 2995 }; 2996 }; 2997 }; 2998 }; 2999 3000 tpda@7862000 { 3001 compatible = "qcom,coresight-tpda", "arm,primecell"; 3002 reg = <0x0 0x07862000 0x0 0x1000>; 3003 3004 clocks = <&aoss_qmp>; 3005 clock-names = "apb_pclk"; 3006 3007 in-ports { 3008 port { 3009 tpda_apss_in: endpoint { 3010 remote-endpoint = <&tpdm_apss_out>; 3011 }; 3012 }; 3013 }; 3014 3015 out-ports { 3016 port { 3017 tpda_apss_out: endpoint { 3018 remote-endpoint = <&funnel_apss_merg_in5>; 3019 }; 3020 }; 3021 }; 3022 }; 3023 3024 tpdm@78a0000 { 3025 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3026 reg = <0x0 0x078a0000 0x0 0x1000>; 3027 3028 clocks = <&aoss_qmp>; 3029 clock-names = "apb_pclk"; 3030 3031 qcom,cmb-element-bits = <32>; 3032 qcom,cmb-msrs-num = <32>; 3033 3034 out-ports { 3035 port { 3036 tpdm_llm_silver_out: endpoint { 3037 remote-endpoint = <&tpda_llm_silver_in>; 3038 }; 3039 }; 3040 }; 3041 }; 3042 3043 tpdm@78b0000 { 3044 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3045 reg = <0x0 0x078b0000 0x0 0x1000>; 3046 3047 clocks = <&aoss_qmp>; 3048 clock-names = "apb_pclk"; 3049 3050 qcom,cmb-element-bits = <32>; 3051 qcom,cmb-msrs-num = <32>; 3052 3053 out-ports { 3054 port { 3055 tpdm_llm_gold_out: endpoint { 3056 remote-endpoint = <&tpda_llm_gold_in>; 3057 }; 3058 }; 3059 }; 3060 }; 3061 3062 tpda@78c0000 { 3063 compatible = "qcom,coresight-tpda", "arm,primecell"; 3064 reg = <0x0 0x078c0000 0x0 0x1000>; 3065 3066 clocks = <&aoss_qmp>; 3067 clock-names = "apb_pclk"; 3068 3069 in-ports { 3070 port { 3071 tpda_llm_silver_in: endpoint { 3072 remote-endpoint = <&tpdm_llm_silver_out>; 3073 }; 3074 }; 3075 }; 3076 3077 out-ports { 3078 port { 3079 tpda_llm_silver_out: endpoint { 3080 remote-endpoint = <&funnel_apss_merg_in3>; 3081 }; 3082 }; 3083 }; 3084 }; 3085 3086 tpda@78d0000 { 3087 compatible = "qcom,coresight-tpda", "arm,primecell"; 3088 reg = <0x0 0x078d0000 0x0 0x1000>; 3089 3090 clocks = <&aoss_qmp>; 3091 clock-names = "apb_pclk"; 3092 3093 in-ports { 3094 port { 3095 tpda_llm_gold_in: endpoint { 3096 remote-endpoint = <&tpdm_llm_gold_out>; 3097 }; 3098 }; 3099 }; 3100 3101 out-ports { 3102 port { 3103 tpda_llm_gold_out: endpoint { 3104 remote-endpoint = <&funnel_apss_merg_in4>; 3105 }; 3106 }; 3107 }; 3108 }; 3109 3110 cti@78e0000 { 3111 compatible = "arm,coresight-cti", "arm,primecell"; 3112 reg = <0x0 0x078e0000 0x0 0x1000>; 3113 3114 clocks = <&aoss_qmp>; 3115 clock-names = "apb_pclk"; 3116 }; 3117 3118 cti@78f0000 { 3119 compatible = "arm,coresight-cti", "arm,primecell"; 3120 reg = <0x0 0x078f0000 0x0 0x1000>; 3121 3122 clocks = <&aoss_qmp>; 3123 clock-names = "apb_pclk"; 3124 }; 3125 3126 cti@7900000 { 3127 compatible = "arm,coresight-cti", "arm,primecell"; 3128 reg = <0x0 0x07900000 0x0 0x1000>; 3129 3130 clocks = <&aoss_qmp>; 3131 clock-names = "apb_pclk"; 3132 }; 3133 3134 remoteproc_cdsp: remoteproc@8300000 { 3135 compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas"; 3136 reg = <0x0 0x08300000 0x0 0x4040>; 3137 3138 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3139 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3140 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3141 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3142 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3143 interrupt-names = "wdog", 3144 "fatal", 3145 "ready", 3146 "handover", 3147 "stop-ack"; 3148 3149 clocks = <&rpmhcc RPMH_CXO_CLK>; 3150 clock-names = "xo"; 3151 3152 power-domains = <&rpmhpd RPMHPD_CX>; 3153 power-domain-names = "cx"; 3154 3155 memory-region = <&rproc_cdsp_mem>; 3156 3157 qcom,qmp = <&aoss_qmp>; 3158 3159 qcom,smem-states = <&cdsp_smp2p_out 0>; 3160 qcom,smem-state-names = "stop"; 3161 3162 status = "disabled"; 3163 3164 glink-edge { 3165 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3166 mboxes = <&apss_shared 4>; 3167 label = "cdsp"; 3168 qcom,remote-pid = <5>; 3169 }; 3170 }; 3171 3172 pmu@90b6300 { 3173 compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon"; 3174 reg = <0x0 0x090b6300 0x0 0x600>; 3175 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3176 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3177 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3178 3179 operating-points-v2 = <&cpu_bwmon_opp_table>; 3180 3181 cpu_bwmon_opp_table: opp-table { 3182 compatible = "operating-points-v2"; 3183 3184 opp-0 { 3185 opp-peak-kBps = <12896000>; 3186 }; 3187 3188 opp-1 { 3189 opp-peak-kBps = <14928000>; 3190 }; 3191 }; 3192 }; 3193 3194 pmu@90cd000 { 3195 compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3196 reg = <0x0 0x090cd000 0x0 0x1000>; 3197 interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>; 3198 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 3199 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3200 3201 operating-points-v2 = <&llcc_bwmon_opp_table>; 3202 3203 llcc_bwmon_opp_table: opp-table { 3204 compatible = "operating-points-v2"; 3205 3206 opp-0 { 3207 opp-peak-kBps = <800000>; 3208 }; 3209 3210 opp-1 { 3211 opp-peak-kBps = <1200000>; 3212 }; 3213 3214 opp-2 { 3215 opp-peak-kBps = <1804800>; 3216 }; 3217 3218 opp-3 { 3219 opp-peak-kBps = <2188800>; 3220 }; 3221 3222 opp-4 { 3223 opp-peak-kBps = <2726400>; 3224 }; 3225 3226 opp-5 { 3227 opp-peak-kBps = <3072000>; 3228 }; 3229 3230 opp-6 { 3231 opp-peak-kBps = <4070400>; 3232 }; 3233 3234 opp-7 { 3235 opp-peak-kBps = <5414400>; 3236 }; 3237 3238 opp-8 { 3239 opp-peak-kBps = <6220800>; 3240 }; 3241 }; 3242 }; 3243 3244 sdhc_2: mmc@8804000 { 3245 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 3246 reg = <0x0 0x08804000 0x0 0x1000>; 3247 reg-names = "hc"; 3248 3249 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3251 interrupt-names = "hc_irq", 3252 "pwr_irq"; 3253 3254 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3255 <&gcc GCC_SDCC2_APPS_CLK>, 3256 <&rpmhcc RPMH_CXO_CLK>; 3257 clock-names = "iface", 3258 "core", 3259 "xo"; 3260 3261 power-domains = <&rpmhpd RPMHPD_CX>; 3262 operating-points-v2 = <&sdhc2_opp_table>; 3263 iommus = <&apps_smmu 0x02a0 0x0>; 3264 resets = <&gcc GCC_SDCC2_BCR>; 3265 interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3266 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3267 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3268 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 3269 interconnect-names = "sdhc-ddr", 3270 "cpu-sdhc"; 3271 3272 qcom,dll-config = <0x0007642c>; 3273 qcom,ddr-config = <0x80040868>; 3274 dma-coherent; 3275 3276 status = "disabled"; 3277 3278 sdhc2_opp_table: opp-table { 3279 compatible = "operating-points-v2"; 3280 3281 opp-50000000 { 3282 opp-hz = /bits/ 64 <50000000>; 3283 required-opps = <&rpmhpd_opp_low_svs>; 3284 }; 3285 3286 opp-100000000 { 3287 opp-hz = /bits/ 64 <100000000>; 3288 required-opps = <&rpmhpd_opp_svs>; 3289 }; 3290 3291 opp-202000000 { 3292 opp-hz = /bits/ 64 <202000000>; 3293 required-opps = <&rpmhpd_opp_nom>; 3294 }; 3295 }; 3296 }; 3297 3298 dc_noc: interconnect@9160000 { 3299 reg = <0x0 0x09160000 0x0 0x3200>; 3300 compatible = "qcom,qcs615-dc-noc"; 3301 #interconnect-cells = <2>; 3302 qcom,bcm-voters = <&apps_bcm_voter>; 3303 }; 3304 3305 llcc: system-cache-controller@9200000 { 3306 compatible = "qcom,qcs615-llcc"; 3307 reg = <0x0 0x09200000 0x0 0x50000>, 3308 <0x0 0x09600000 0x0 0x50000>; 3309 reg-names = "llcc0_base", 3310 "llcc_broadcast_base"; 3311 }; 3312 3313 gem_noc: interconnect@9680000 { 3314 reg = <0x0 0x09680000 0x0 0x3e200>; 3315 compatible = "qcom,qcs615-gem-noc"; 3316 #interconnect-cells = <2>; 3317 qcom,bcm-voters = <&apps_bcm_voter>; 3318 }; 3319 3320 pdc: interrupt-controller@b220000 { 3321 compatible = "qcom,qcs615-pdc", "qcom,pdc"; 3322 reg = <0x0 0x0b220000 0x0 0x30000>, 3323 <0x0 0x17c000f0 0x0 0x64>; 3324 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3325 interrupt-parent = <&intc>; 3326 #interrupt-cells = <2>; 3327 interrupt-controller; 3328 }; 3329 3330 aoss_qmp: power-management@c300000 { 3331 compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp"; 3332 reg = <0x0 0x0c300000 0x0 0x400>; 3333 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3334 mboxes = <&apss_shared 0>; 3335 3336 #clock-cells = <0>; 3337 }; 3338 3339 sram@c3f0000 { 3340 compatible = "qcom,rpmh-stats"; 3341 reg = <0x0 0x0c3f0000 0x0 0x400>; 3342 }; 3343 3344 sram@14680000 { 3345 compatible = "qcom,qcs615-imem", "syscon", "simple-mfd"; 3346 reg = <0x0 0x14680000 0x0 0x2c000>; 3347 ranges = <0 0 0x14680000 0x2c000>; 3348 3349 #address-cells = <1>; 3350 #size-cells = <1>; 3351 3352 pil-reloc@2a94c { 3353 compatible = "qcom,pil-reloc-info"; 3354 reg = <0x2a94c 0xc8>; 3355 }; 3356 }; 3357 3358 apps_smmu: iommu@15000000 { 3359 compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3360 reg = <0x0 0x15000000 0x0 0x80000>; 3361 #iommu-cells = <2>; 3362 #global-interrupts = <1>; 3363 dma-coherent; 3364 3365 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3397 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3398 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3399 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3400 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3401 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3402 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3403 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3404 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3405 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3406 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3407 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3408 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3409 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3410 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3411 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3412 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3413 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3414 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3415 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3417 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3418 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3419 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3421 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3422 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3423 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3424 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3425 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3426 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3427 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3428 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3429 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 3430 }; 3431 3432 spmi_bus: spmi@c440000 { 3433 compatible = "qcom,spmi-pmic-arb"; 3434 reg = <0x0 0x0c440000 0x0 0x1100>, 3435 <0x0 0x0c600000 0x0 0x2000000>, 3436 <0x0 0x0e600000 0x0 0x100000>, 3437 <0x0 0x0e700000 0x0 0xa0000>, 3438 <0x0 0x0c40a000 0x0 0x26000>; 3439 reg-names = "core", 3440 "chnls", 3441 "obsrvr", 3442 "intr", 3443 "cnfg"; 3444 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3445 interrupt-names = "periph_irq"; 3446 interrupt-controller; 3447 #interrupt-cells = <4>; 3448 #address-cells = <2>; 3449 #size-cells = <0>; 3450 qcom,channel = <0>; 3451 qcom,ee = <0>; 3452 }; 3453 3454 intc: interrupt-controller@17a00000 { 3455 compatible = "arm,gic-v3"; 3456 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3457 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3458 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3459 #interrupt-cells = <3>; 3460 interrupt-controller; 3461 #redistributor-regions = <1>; 3462 redistributor-stride = <0x0 0x20000>; 3463 }; 3464 3465 apss_shared: mailbox@17c00000 { 3466 compatible = "qcom,qcs615-apss-shared", 3467 "qcom,sdm845-apss-shared"; 3468 reg = <0x0 0x17c00000 0x0 0x1000>; 3469 #mbox-cells = <1>; 3470 }; 3471 3472 watchdog: watchdog@17c10000 { 3473 compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt"; 3474 reg = <0x0 0x17c10000 0x0 0x1000>; 3475 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3476 }; 3477 3478 timer@17c20000 { 3479 compatible = "arm,armv7-timer-mem"; 3480 reg = <0x0 0x17c20000 0x0 0x1000>; 3481 ranges = <0 0 0 0x20000000>; 3482 #address-cells = <1>; 3483 #size-cells = <1>; 3484 3485 frame@17c21000 { 3486 reg = <0x17c21000 0x1000>, 3487 <0x17c22000 0x1000>; 3488 frame-number = <0>; 3489 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3491 }; 3492 3493 frame@17c23000 { 3494 reg = <0x17c23000 0x1000>; 3495 frame-number = <1>; 3496 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3497 status = "disabled"; 3498 }; 3499 3500 frame@17c25000 { 3501 reg = <0x17c25000 0x1000>; 3502 frame-number = <2>; 3503 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3504 status = "disabled"; 3505 }; 3506 3507 frame@17c27000 { 3508 reg = <0x17c27000 0x1000>; 3509 frame-number = <3>; 3510 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3511 status = "disabled"; 3512 }; 3513 3514 frame@17c29000 { 3515 reg = <0x17c29000 0x1000>; 3516 frame-number = <4>; 3517 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3518 status = "disabled"; 3519 }; 3520 3521 frame@17c2b000 { 3522 reg = <0x17c2b000 0x1000>; 3523 frame-number = <5>; 3524 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3525 status = "disabled"; 3526 }; 3527 3528 frame@17c2d000 { 3529 reg = <0x17c2d000 0x1000>; 3530 frame-number = <6>; 3531 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3532 status = "disabled"; 3533 }; 3534 }; 3535 3536 apps_rsc: rsc@18200000 { 3537 compatible = "qcom,rpmh-rsc"; 3538 reg = <0x0 0x18200000 0x0 0x10000>, 3539 <0x0 0x18210000 0x0 0x10000>, 3540 <0x0 0x18220000 0x0 0x10000>; 3541 reg-names = "drv-0", 3542 "drv-1", 3543 "drv-2"; 3544 3545 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3546 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3547 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3548 3549 qcom,drv-id = <2>; 3550 qcom,tcs-offset = <0xd00>; 3551 qcom,tcs-config = <ACTIVE_TCS 2>, 3552 <SLEEP_TCS 3>, 3553 <WAKE_TCS 3>, 3554 <CONTROL_TCS 1>; 3555 3556 label = "apps_rsc"; 3557 power-domains = <&cluster_pd>; 3558 3559 apps_bcm_voter: bcm-voter { 3560 compatible = "qcom,bcm-voter"; 3561 }; 3562 3563 rpmhcc: clock-controller { 3564 compatible = "qcom,qcs615-rpmh-clk"; 3565 clock-names = "xo"; 3566 3567 #clock-cells = <1>; 3568 }; 3569 3570 rpmhpd: power-controller { 3571 compatible = "qcom,qcs615-rpmhpd"; 3572 #power-domain-cells = <1>; 3573 operating-points-v2 = <&rpmhpd_opp_table>; 3574 3575 rpmhpd_opp_table: opp-table { 3576 compatible = "operating-points-v2"; 3577 3578 rpmhpd_opp_ret: opp-0 { 3579 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3580 }; 3581 3582 rpmhpd_opp_min_svs: opp-1 { 3583 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3584 }; 3585 3586 rpmhpd_opp_low_svs: opp-2 { 3587 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3588 }; 3589 3590 rpmhpd_opp_svs: opp-3 { 3591 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3592 }; 3593 3594 rpmhpd_opp_svs_l1: opp-4 { 3595 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3596 }; 3597 3598 rpmhpd_opp_nom: opp-5 { 3599 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3600 }; 3601 3602 rpmhpd_opp_nom_l1: opp-6 { 3603 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3604 }; 3605 3606 rpmhpd_opp_nom_l2: opp-7 { 3607 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3608 }; 3609 3610 rpmhpd_opp_turbo: opp-8 { 3611 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3612 }; 3613 3614 rpmhpd_opp_turbo_l1: opp-9 { 3615 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3616 }; 3617 }; 3618 }; 3619 }; 3620 3621 usb_1_hsphy: phy@88e2000 { 3622 compatible = "qcom,qcs615-qusb2-phy"; 3623 reg = <0x0 0x88e2000 0x0 0x180>; 3624 3625 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>; 3626 clock-names = "cfg_ahb", "ref"; 3627 3628 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3629 nvmem-cells = <&qusb2_hstx_trim>; 3630 3631 #phy-cells = <0>; 3632 3633 status = "disabled"; 3634 }; 3635 3636 usb_hsphy_2: phy@88e3000 { 3637 compatible = "qcom,qcs615-qusb2-phy"; 3638 reg = <0x0 0x088e3000 0x0 0x180>; 3639 3640 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, 3641 <&rpmhcc RPMH_CXO_CLK>; 3642 clock-names = "cfg_ahb", 3643 "ref"; 3644 3645 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3646 3647 #phy-cells = <0>; 3648 3649 status = "disabled"; 3650 }; 3651 3652 usb_qmpphy: phy@88e6000 { 3653 compatible = "qcom,qcs615-qmp-usb3-phy"; 3654 reg = <0x0 0x88e6000 0x0 0x1000>; 3655 3656 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3657 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3658 <&gcc GCC_AHB2PHY_WEST_CLK>, 3659 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3660 clock-names = "aux", 3661 "ref", 3662 "cfg_ahb", 3663 "pipe"; 3664 3665 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 3666 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 3667 reset-names = "phy", "phy_phy"; 3668 3669 qcom,tcsr-reg = <&tcsr 0xb244>; 3670 3671 clock-output-names = "usb3_phy_pipe_clk_src"; 3672 #clock-cells = <0>; 3673 3674 #phy-cells = <0>; 3675 3676 status = "disabled"; 3677 }; 3678 3679 usb_1: usb@a6f8800 { 3680 compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; 3681 reg = <0x0 0x0a6f8800 0x0 0x400>; 3682 3683 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3684 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3685 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3686 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3687 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3688 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 3689 clock-names = "cfg_noc", 3690 "core", 3691 "iface", 3692 "sleep", 3693 "mock_utmi", 3694 "xo"; 3695 3696 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3697 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3698 assigned-clock-rates = <19200000>, <200000000>; 3699 3700 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3701 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3702 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 3703 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3704 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 3705 interrupt-names = "pwr_event", 3706 "hs_phy_irq", 3707 "dp_hs_phy_irq", 3708 "dm_hs_phy_irq", 3709 "ss_phy_irq"; 3710 3711 power-domains = <&gcc USB30_PRIM_GDSC>; 3712 required-opps = <&rpmhpd_opp_nom>; 3713 3714 resets = <&gcc GCC_USB30_PRIM_BCR>; 3715 3716 #address-cells = <2>; 3717 #size-cells = <2>; 3718 ranges; 3719 3720 status = "disabled"; 3721 3722 usb_1_dwc3: usb@a600000 { 3723 compatible = "snps,dwc3"; 3724 reg = <0x0 0x0a600000 0x0 0xcd00>; 3725 3726 iommus = <&apps_smmu 0x140 0x0>; 3727 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3728 3729 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 3730 phy-names = "usb2-phy", "usb3-phy"; 3731 3732 snps,dis-u1-entry-quirk; 3733 snps,dis-u2-entry-quirk; 3734 snps,dis_u2_susphy_quirk; 3735 snps,dis_u3_susphy_quirk; 3736 snps,dis_enblslpm_quirk; 3737 snps,has-lpm-erratum; 3738 snps,hird-threshold = /bits/ 8 <0x10>; 3739 snps,usb3_lpm_capable; 3740 }; 3741 }; 3742 3743 usb_2: usb@a8f8800 { 3744 compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; 3745 reg = <0x0 0x0a8f8800 0x0 0x400>; 3746 3747 clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, 3748 <&gcc GCC_USB20_SEC_MASTER_CLK>, 3749 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, 3750 <&gcc GCC_USB20_SEC_SLEEP_CLK>, 3751 <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 3752 <&gcc GCC_USB2_PRIM_CLKREF_CLK>; 3753 clock-names = "cfg_noc", 3754 "core", 3755 "iface", 3756 "sleep", 3757 "mock_utmi", 3758 "xo"; 3759 3760 assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 3761 <&gcc GCC_USB20_SEC_MASTER_CLK>; 3762 assigned-clock-rates = <19200000>, <200000000>; 3763 3764 interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>, 3765 <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 3766 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 3767 <&pdc 10 IRQ_TYPE_EDGE_BOTH>; 3768 interrupt-names = "pwr_event", 3769 "hs_phy_irq", 3770 "dp_hs_phy_irq", 3771 "dm_hs_phy_irq"; 3772 3773 power-domains = <&gcc USB20_SEC_GDSC>; 3774 required-opps = <&rpmhpd_opp_nom>; 3775 3776 resets = <&gcc GCC_USB20_SEC_BCR>; 3777 3778 qcom,select-utmi-as-pipe-clk; 3779 3780 #address-cells = <2>; 3781 #size-cells = <2>; 3782 ranges; 3783 3784 status = "disabled"; 3785 3786 usb_2_dwc3: usb@a800000 { 3787 compatible = "snps,dwc3"; 3788 reg = <0x0 0x0a800000 0x0 0xcd00>; 3789 3790 iommus = <&apps_smmu 0xe0 0x0>; 3791 interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>; 3792 3793 phys = <&usb_hsphy_2>; 3794 phy-names = "usb2-phy"; 3795 3796 snps,dis_u2_susphy_quirk; 3797 snps,dis_u3_susphy_quirk; 3798 snps,dis_enblslpm_quirk; 3799 snps,has-lpm-erratum; 3800 snps,hird-threshold = /bits/ 8 <0x10>; 3801 3802 maximum-speed = "high-speed"; 3803 }; 3804 }; 3805 3806 remoteproc_adsp: remoteproc@62400000 { 3807 compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas"; 3808 reg = <0x0 0x62400000 0x0 0x4040>; 3809 3810 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3811 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3812 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3813 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3814 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3815 interrupt-names = "wdog", 3816 "fatal", 3817 "ready", 3818 "handover", 3819 "stop-ack"; 3820 3821 clocks = <&rpmhcc RPMH_CXO_CLK>; 3822 clock-names = "xo"; 3823 3824 power-domains = <&rpmhpd RPMHPD_CX>; 3825 power-domain-names = "cx"; 3826 3827 memory-region = <&rproc_adsp_mem>; 3828 3829 qcom,qmp = <&aoss_qmp>; 3830 3831 qcom,smem-states = <&adsp_smp2p_out 0>; 3832 qcom,smem-state-names = "stop"; 3833 3834 status = "disabled"; 3835 3836 glink_edge: glink-edge { 3837 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 3838 mboxes = <&apss_shared 24>; 3839 label = "lpass"; 3840 qcom,remote-pid = <2>; 3841 }; 3842 }; 3843 }; 3844 3845 arch_timer: timer { 3846 compatible = "arm,armv8-timer"; 3847 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3848 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3849 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3850 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3851 }; 3852}; 3853