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Searched +full:dphy +full:- +full:cfg (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/phy/cadence/
H A Dcdns-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright: 2017-2018 Cadence Design Systems, Inc.
17 #include <linux/phy/phy-mipi-dphy.h>
23 /* DPHY registers */
88 int (*probe)(struct cdns_dphy *dphy);
89 void (*remove)(struct cdns_dphy *dphy);
90 void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
91 void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
92 enum cdns_dphy_clk_lane_cfg cfg);
93 void (*set_pll_cfg)(struct cdns_dphy *dphy,
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/linux/Documentation/devicetree/bindings/phy/
H A Drockchip-mipi-dphy-rx0.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
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H A Dstarfive,jh7110-dphy-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive SoC JH7110 MIPI D-PHY Rx Controller
10 - Jack Zhu <jack.zhu@starfivetech.com>
11 - Changhuang Liang <changhuang.liang@starfivetech.com>
14 StarFive SoCs contain a MIPI CSI D-PHY based on M31 IP, used to
19 const: starfive,jh7110-dphy-rx
26 - description: config clock
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/clk-provider.h>
22 #include <dt-bindings/firmware/imx/rsrc.h>
35 /* DPHY registers */
63 ((x) < 32) ? 0xe0 | ((x) - 16) : \
64 ((x) < 64) ? 0xc0 | ((x) - 32) : \
65 ((x) < 128) ? 0x80 | ((x) - 64) : \
66 ((x) - 128))
67 #define CN(x) (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f))
68 #define CO(x) ((CO_BUF) >> (8 - (x)) & 0x03)
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/linux/drivers/phy/starfive/
H A Dphy-jh7110-dphy-rx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive JH7110 DPHY RX driver
75 struct stf_dphy *dphy = phy_get_drvdata(phy); in stf_dphy_configure() local
76 const struct stf_dphy_info *info = dphy->info; in stf_dphy_configure()
84 FIELD_PREP(STF_DPHY_LANE_SWAP_CLK, info->maps[0]) | in stf_dphy_configure()
85 FIELD_PREP(STF_DPHY_LANE_SWAP_CLK1, info->maps[5]) | in stf_dphy_configure()
86 FIELD_PREP(STF_DPHY_LANE_SWAP_LAN0, info->maps[1]) | in stf_dphy_configure()
87 FIELD_PREP(STF_DPHY_LANE_SWAP_LAN1, info->maps[2]), in stf_dphy_configure()
88 dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(188)); in stf_dphy_configure()
90 writel(FIELD_PREP(STF_DPHY_LANE_SWAP_LAN2, info->maps[3]) | in stf_dphy_configure()
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/linux/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-csi.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip ISP1 Driver - CSI-2 Receiver
16 #include <linux/phy/phy-mipi-dphy.h>
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-fwnode.h>
21 #include "rkisp1-common.h"
22 #include "rkisp1-csi.h"
37 struct rkisp1_csi *csi = &rkisp1->csi; in rkisp1_csi_link_sensor()
40 s_asd->pixel_rate_ctrl = v4l2_ctrl_find(sd->ctrl_handler, in rkisp1_csi_link_sensor()
42 if (!s_asd->pixel_rate_ctrl) { in rkisp1_csi_link_sensor()
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/linux/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3528-ioc-grf
19 - rockchip,rk3528-pipe-phy-grf
20 - rockchip,rk3528-vo-grf
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/linux/drivers/phy/
H A Dphy-core-mipi-dphy.c1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/phy/phy-mipi-dphy.h>
16 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
18 * of the D-PHY specification (v1.2).
24 struct phy_configure_opts_mipi_dphy *cfg) in phy_mipi_dphy_calc_config() argument
28 if (!cfg) in phy_mipi_dphy_calc_config()
29 return -EINVAL; in phy_mipi_dphy_calc_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_calc_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_calc_config()
41 cfg->clk_pre = 8; in phy_mipi_dphy_calc_config()
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/linux/drivers/phy/rockchip/
H A Dphy-rockchip-dphy-rx0.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip MIPI Synopsys DPHY RX0 driver
11 * chromeos-4.4 branch.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
25 #include <linux/phy/phy-mipi-dphy.h>
64 "dphy-ref",
65 "dphy-cfg",
110 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
162 const struct dphy_reg *reg = &priv->drv_data->regs[index]; in rk_dphy_write_grf()
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/linux/drivers/gpu/drm/kmb/
H A Dkmb_dsi.h1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2019-2020 Intel Corporation
12 /* MIPI TX CFG */
18 /* DPHY Tx test codes*/
43 /* DPHY params */
58 /* 2 Data Lanes per D-PHY */
81 /* DPHY Tx test codes */
341 writel(value, (kmb_dsi->mipi_mmio + reg)); in kmb_write_mipi()
346 return readl(kmb_dsi->mipi_mmio + reg); in kmb_read_mipi()
354 u32 mask = (1 << num_bits) - 1; in kmb_write_bits_mipi()
/linux/drivers/gpu/drm/sun4i/
H A Dsun6i_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
11 #include <linux/crc-ccitt.h>
14 #include <linux/phy/phy-mipi-dphy.h>
293 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_abort()
299 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_commit()
308 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_wait_for_completion()
321 regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id), in sun6i_dsi_inst_setup()
332 u8 lanes_mask = GENMASK(device->lanes - 1, 0); in sun6i_dsi_inst_init()
359 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_CFG_REG(0), in sun6i_dsi_inst_init()
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/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-isys-mcd-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013--2024 Intel Corporation
14 #include <media/v4l2-async.h>
17 #include "ipu6-bus.h"
18 #include "ipu6-isys.h"
19 #include "ipu6-isys-csi2.h"
20 #include "ipu6-platform-isys-csi2-reg.h"
38 * There are 2 MCD DPHY instances on TGL and 1 MCD DPHY instance on ADL.
39 * Each MCD PHY has 12-lanes which has 8 data lanes and 4 clock lanes.
44 * +---------+---------+---------+---------+--------+---------+----------+
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/linux/drivers/pmdomain/starfive/
H A Djh71xx-pmu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
15 #include <dt-bindings/power/starfive,jh7110-pmu.h>
29 /* sw encourage cfg */
87 struct jh71xx_pmu *pmu = pmd->pmu; in jh71xx_pmu_get_state()
90 return -EINVAL; in jh71xx_pmu_get_state()
92 *is_on = readl(pmu->base + pmu->match_data->pmu_status) & mask; in jh71xx_pmu_get_state()
99 struct jh71xx_pmu *pmu = pmd->pmu; in jh7110_pmu_set_state()
107 spin_lock_irqsave(&pmu->lock, flags); in jh7110_pmu_set_state()
129 writel(mask, pmu->base + mode); in jh7110_pmu_set_state()
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/linux/drivers/phy/allwinner/
H A Dphy-sun4i-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2014-2015 Hans de Goede <hdegoede@redhat.com>
10 * Modelled after: Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY driver
18 #include <linux/extcon-provider.h>
27 #include <linux/phy/phy-sun4i-usb.h>
114 const struct sun4i_usb_phy_cfg *cfg; member
145 container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
153 iscr = readl(data->base + REG_ISCR); in sun4i_usb_phy0_update_iscr()
156 writel(iscr, data->base + REG_ISCR); in sun4i_usb_phy0_update_iscr()
183 u32 temp, usbc_bit = BIT(phy->index * 2); in sun4i_usb_phy_write()
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/linux/drivers/media/i2c/
H A Dtc358746.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TC358746 - Parallel <-> CSI-2 Bridge
8 * - Currently only 'Parallel-in -> CSI-out' mode is supported!
13 #include <linux/clk-provider.h>
19 #include <linux/phy/phy-mipi-dphy.h>
24 #include <media/v4l2-ctrls.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-fwnode.h>
27 #include <media/v4l2-mc.h>
29 /* 16-bit registers */
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/linux/drivers/clk/sprd/
H A Dsc9863a-clk.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
26 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94,
28 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
30 static SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c,
32 static SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,
34 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc,
36 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0,
38 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4,
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-librem5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 Purism SPC
6 /dts-v1/;
8 #include "dt-bindings/input/input.h"
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include "dt-bindings/pwm/pwm.h"
12 #include "dt-bindings/usb/pd.h"
18 chassis-type = "handset";
20 backlight_dsi: backlight-dsi {
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/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h>
13 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
14 #include <dt-bindings/thermal/thermal.h>
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
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