1 // SPDX-License-Identifier: GPL-2.0
5  * Author: Wyon Bi <bivvy.bi@rock-chips.com>
12 #include <linux/clk-provider.h>
24 #include <linux/phy/phy-mipi-dphy.h>
330 	orig = readl(inno->phy_base + reg);  in phy_update_bits()
333 	writel(tmp, inno->phy_base + reg);  in phy_update_bits()
339 	unsigned long prate = clk_get_rate(inno->ref_clk);  in inno_dsidphy_pll_calc_rate()
350 	 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2  in inno_dsidphy_pll_calc_rate()
383 		delta = abs(fout - tmp);  in inno_dsidphy_pll_calc_rate()
398 		inno->pll.prediv = best_prediv;  in inno_dsidphy_pll_calc_rate()
399 		inno->pll.fbdiv = best_fbdiv;  in inno_dsidphy_pll_calc_rate()
400 		inno->pll.rate = best_freq;  in inno_dsidphy_pll_calc_rate()
408 	struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg;  in inno_dsidphy_mipi_mode_enable()  local
417 	timings = inno->pdata->inno_mipi_dphy_timing_table;  in inno_dsidphy_mipi_mode_enable()
419 	inno_dsidphy_pll_calc_rate(inno, cfg->hs_clk_rate);  in inno_dsidphy_mipi_mode_enable()
426 			REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));  in inno_dsidphy_mipi_mode_enable()
428 			REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv));  in inno_dsidphy_mipi_mode_enable()
430 			REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));  in inno_dsidphy_mipi_mode_enable()
431 	if (inno->pdata->max_rate == MAX_2_5GHZ) {  in inno_dsidphy_mipi_mode_enable()
437 	} else if (inno->pdata->max_rate == MAX_1_5GHZ) {  in inno_dsidphy_mipi_mode_enable()
472 	txbyteclkhs = inno->pll.rate / 8;  in inno_dsidphy_mipi_mode_enable()
480 	 * The value of counter for HS Ths-exit  in inno_dsidphy_mipi_mode_enable()
481 	 * Ths-exit = Tpin_txbyteclkhs * value  in inno_dsidphy_mipi_mode_enable()
483 	hs_exit = DIV_ROUND_UP(cfg->hs_exit, t_txbyteclkhs);  in inno_dsidphy_mipi_mode_enable()
485 	 * The value of counter for HS Tclk-post  in inno_dsidphy_mipi_mode_enable()
486 	 * Tclk-post = Tpin_txbyteclkhs * value  in inno_dsidphy_mipi_mode_enable()
488 	clk_post = DIV_ROUND_UP(cfg->clk_post, t_txbyteclkhs);  in inno_dsidphy_mipi_mode_enable()
490 	 * The value of counter for HS Tclk-pre  in inno_dsidphy_mipi_mode_enable()
491 	 * Tclk-pre = Tpin_txbyteclkhs * value  in inno_dsidphy_mipi_mode_enable()
493 	clk_pre = DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE);  in inno_dsidphy_mipi_mode_enable()
496 	 * The value of counter for HS Tta-go  in inno_dsidphy_mipi_mode_enable()
497 	 * Tta-go for turnaround  in inno_dsidphy_mipi_mode_enable()
498 	 * Tta-go = Ttxclkesc * value  in inno_dsidphy_mipi_mode_enable()
500 	ta_go = DIV_ROUND_UP(cfg->ta_go, t_txclkesc);  in inno_dsidphy_mipi_mode_enable()
502 	 * The value of counter for HS Tta-sure  in inno_dsidphy_mipi_mode_enable()
503 	 * Tta-sure for turnaround  in inno_dsidphy_mipi_mode_enable()
504 	 * Tta-sure = Ttxclkesc * value  in inno_dsidphy_mipi_mode_enable()
506 	ta_sure = DIV_ROUND_UP(cfg->ta_sure, t_txclkesc);  in inno_dsidphy_mipi_mode_enable()
508 	 * The value of counter for HS Tta-wait  in inno_dsidphy_mipi_mode_enable()
509 	 * Tta-wait for turnaround  in inno_dsidphy_mipi_mode_enable()
510 	 * Tta-wait = Ttxclkesc * value  in inno_dsidphy_mipi_mode_enable()
512 	ta_wait = DIV_ROUND_UP(cfg->ta_get, t_txclkesc);  in inno_dsidphy_mipi_mode_enable()
514 	for (i = 0; i < inno->pdata->num_timings; i++)  in inno_dsidphy_mipi_mode_enable()
515 		if (inno->pll.rate <= timings[i].rate)  in inno_dsidphy_mipi_mode_enable()
518 	if (i == inno->pdata->num_timings)  in inno_dsidphy_mipi_mode_enable()
519 		--i;  in inno_dsidphy_mipi_mode_enable()
525 	if (inno->pdata->max_rate == MAX_1GHZ) {  in inno_dsidphy_mipi_mode_enable()
526 		lpx = DIV_ROUND_UP(cfg->lpx, t_txbyteclkhs);  in inno_dsidphy_mipi_mode_enable()
528 			lpx -= 2;  in inno_dsidphy_mipi_mode_enable()
548 		if (inno->pdata->max_rate == MAX_2_5GHZ)  in inno_dsidphy_mipi_mode_enable()
555 		if (inno->pdata->max_rate == MAX_2_5GHZ)  in inno_dsidphy_mipi_mode_enable()
560 		if (inno->pdata->max_rate == MAX_2_5GHZ)  in inno_dsidphy_mipi_mode_enable()
580 	switch (inno->pdata->max_lanes) {  in inno_dsidphy_mipi_mode_enable()
656 	clk_prepare_enable(inno->pclk_phy);  in inno_dsidphy_power_on()
657 	clk_prepare_enable(inno->ref_clk);  in inno_dsidphy_power_on()
658 	pm_runtime_get_sync(inno->dev);  in inno_dsidphy_power_on()
667 	switch (inno->mode) {  in inno_dsidphy_power_on()
675 		return -EINVAL;  in inno_dsidphy_power_on()
702 	pm_runtime_put(inno->dev);  in inno_dsidphy_power_off()
703 	clk_disable_unprepare(inno->ref_clk);  in inno_dsidphy_power_off()
704 	clk_disable_unprepare(inno->pclk_phy);  in inno_dsidphy_power_off()
717 		inno->mode = mode;  in inno_dsidphy_set_mode()
720 		return -EINVAL;  in inno_dsidphy_set_mode()
732 	if (inno->mode != PHY_MODE_MIPI_DPHY)  in inno_dsidphy_configure()
733 		return -EINVAL;  in inno_dsidphy_configure()
735 	ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);  in inno_dsidphy_configure()
739 	memcpy(&inno->dphy_cfg, &opts->mipi_dphy, sizeof(inno->dphy_cfg));  in inno_dsidphy_configure()
775 	struct device *dev = &pdev->dev;  in inno_dsidphy_probe()
783 		return -ENOMEM;  in inno_dsidphy_probe()
785 	inno->dev = dev;  in inno_dsidphy_probe()
786 	inno->pdata = of_device_get_match_data(inno->dev);  in inno_dsidphy_probe()
789 	inno->phy_base = devm_platform_ioremap_resource(pdev, 0);  in inno_dsidphy_probe()
790 	if (IS_ERR(inno->phy_base))  in inno_dsidphy_probe()
791 		return PTR_ERR(inno->phy_base);  in inno_dsidphy_probe()
793 	inno->ref_clk = devm_clk_get(dev, "ref");  in inno_dsidphy_probe()
794 	if (IS_ERR(inno->ref_clk)) {  in inno_dsidphy_probe()
795 		ret = PTR_ERR(inno->ref_clk);  in inno_dsidphy_probe()
800 	inno->pclk_phy = devm_clk_get(dev, "pclk");  in inno_dsidphy_probe()
801 	if (IS_ERR(inno->pclk_phy)) {  in inno_dsidphy_probe()
802 		ret = PTR_ERR(inno->pclk_phy);  in inno_dsidphy_probe()
807 	inno->rst = devm_reset_control_get(dev, "apb");  in inno_dsidphy_probe()
808 	if (IS_ERR(inno->rst)) {  in inno_dsidphy_probe()
809 		ret = PTR_ERR(inno->rst);  in inno_dsidphy_probe()
839 	pm_runtime_disable(inno->dev);  in inno_dsidphy_remove()
844 		.compatible = "rockchip,px30-dsi-dphy",
847 		.compatible = "rockchip,rk3128-dsi-dphy",
850 		.compatible = "rockchip,rk3368-dsi-dphy",
853 		.compatible = "rockchip,rk3506-dsi-dphy",
856 		.compatible = "rockchip,rk3568-dsi-dphy",
859 		.compatible = "rockchip,rv1126-dsi-dphy",
868 		.name = "inno-dsidphy",
876 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");