1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/axg-aoclkc.h> 7#include <dt-bindings/clock/axg-audio-clkc.h> 8#include <dt-bindings/clock/axg-clkc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/meson-axg-gpio.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 15#include <dt-bindings/power/meson-axg-power.h> 16 17/ { 18 compatible = "amlogic,meson-axg"; 19 20 interrupt-parent = <&gic>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 tdmif_a: audio-controller-0 { 25 compatible = "amlogic,axg-tdm-iface"; 26 #sound-dai-cells = <0>; 27 sound-name-prefix = "TDM_A"; 28 clocks = <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>, 30 <&clkc_audio AUD_CLKID_MST_A_MCLK>; 31 clock-names = "sclk", "lrclk", "mclk"; 32 status = "disabled"; 33 }; 34 35 tdmif_b: audio-controller-1 { 36 compatible = "amlogic,axg-tdm-iface"; 37 #sound-dai-cells = <0>; 38 sound-name-prefix = "TDM_B"; 39 clocks = <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>, 41 <&clkc_audio AUD_CLKID_MST_B_MCLK>; 42 clock-names = "sclk", "lrclk", "mclk"; 43 status = "disabled"; 44 }; 45 46 tdmif_c: audio-controller-2 { 47 compatible = "amlogic,axg-tdm-iface"; 48 #sound-dai-cells = <0>; 49 sound-name-prefix = "TDM_C"; 50 clocks = <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>, 52 <&clkc_audio AUD_CLKID_MST_C_MCLK>; 53 clock-names = "sclk", "lrclk", "mclk"; 54 status = "disabled"; 55 }; 56 57 arm-pmu { 58 compatible = "arm,cortex-a53-pmu"; 59 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 63 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 64 }; 65 66 cpus { 67 #address-cells = <0x2>; 68 #size-cells = <0x0>; 69 70 cpu0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x0 0x0>; 74 enable-method = "psci"; 75 next-level-cache = <&l2>; 76 clocks = <&scpi_dvfs 0>; 77 dynamic-power-coefficient = <140>; 78 #cooling-cells = <2>; 79 }; 80 81 cpu1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x1>; 85 enable-method = "psci"; 86 next-level-cache = <&l2>; 87 clocks = <&scpi_dvfs 0>; 88 dynamic-power-coefficient = <140>; 89 #cooling-cells = <2>; 90 }; 91 92 cpu2: cpu@2 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a53"; 95 reg = <0x0 0x2>; 96 enable-method = "psci"; 97 next-level-cache = <&l2>; 98 clocks = <&scpi_dvfs 0>; 99 dynamic-power-coefficient = <140>; 100 #cooling-cells = <2>; 101 }; 102 103 cpu3: cpu@3 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a53"; 106 reg = <0x0 0x3>; 107 enable-method = "psci"; 108 next-level-cache = <&l2>; 109 clocks = <&scpi_dvfs 0>; 110 dynamic-power-coefficient = <140>; 111 #cooling-cells = <2>; 112 }; 113 114 l2: l2-cache0 { 115 compatible = "cache"; 116 cache-level = <2>; 117 cache-unified; 118 }; 119 }; 120 121 sm: secure-monitor { 122 compatible = "amlogic,meson-gxbb-sm"; 123 }; 124 125 efuse: efuse { 126 compatible = "amlogic,meson-gxbb-efuse"; 127 clocks = <&clkc CLKID_EFUSE>; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 read-only; 131 secure-monitor = <&sm>; 132 }; 133 134 psci { 135 compatible = "arm,psci-1.0"; 136 method = "smc"; 137 }; 138 139 reserved-memory { 140 #address-cells = <2>; 141 #size-cells = <2>; 142 ranges; 143 144 /* 16 MiB reserved for Hardware ROM Firmware */ 145 hwrom_reserved: hwrom@0 { 146 reg = <0x0 0x0 0x0 0x1000000>; 147 no-map; 148 }; 149 150 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 151 secmon_reserved: secmon@5000000 { 152 reg = <0x0 0x05000000 0x0 0x300000>; 153 no-map; 154 }; 155 }; 156 157 scpi { 158 compatible = "arm,scpi-pre-1.0"; 159 mboxes = <&mailbox 1 &mailbox 2>; 160 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 161 162 scpi_clocks: clocks { 163 compatible = "arm,scpi-clocks"; 164 165 scpi_dvfs: clocks-0 { 166 compatible = "arm,scpi-dvfs-clocks"; 167 #clock-cells = <1>; 168 clock-indices = <0>; 169 clock-output-names = "vcpu"; 170 }; 171 }; 172 173 scpi_sensors: sensors { 174 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; 175 #thermal-sensor-cells = <1>; 176 }; 177 }; 178 179 soc { 180 compatible = "simple-bus"; 181 #address-cells = <2>; 182 #size-cells = <2>; 183 ranges; 184 185 pcieA: pcie@f9800000 { 186 compatible = "amlogic,axg-pcie", "snps,dw-pcie"; 187 reg = <0x0 0xf9800000 0x0 0x400000>, 188 <0x0 0xff646000 0x0 0x2000>, 189 <0x0 0xf9f00000 0x0 0x100000>; 190 reg-names = "elbi", "cfg", "config"; 191 interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; 192 #interrupt-cells = <1>; 193 interrupt-map-mask = <0 0 0 0>; 194 interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 195 bus-range = <0x0 0xff>; 196 #address-cells = <3>; 197 #size-cells = <2>; 198 device_type = "pci"; 199 ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>; 200 201 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>; 202 clock-names = "general", "pclk", "port"; 203 resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>; 204 reset-names = "port", "apb"; 205 num-lanes = <1>; 206 phys = <&pcie_phy>; 207 phy-names = "pcie"; 208 status = "disabled"; 209 }; 210 211 pcieB: pcie@fa000000 { 212 compatible = "amlogic,axg-pcie", "snps,dw-pcie"; 213 reg = <0x0 0xfa000000 0x0 0x400000>, 214 <0x0 0xff648000 0x0 0x2000>, 215 <0x0 0xfa400000 0x0 0x100000>; 216 reg-names = "elbi", "cfg", "config"; 217 interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>; 218 #interrupt-cells = <1>; 219 interrupt-map-mask = <0 0 0 0>; 220 interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; 221 bus-range = <0x0 0xff>; 222 #address-cells = <3>; 223 #size-cells = <2>; 224 device_type = "pci"; 225 ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>; 226 227 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>; 228 clock-names = "general", "pclk", "port"; 229 resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>; 230 reset-names = "port", "apb"; 231 num-lanes = <1>; 232 phys = <&pcie_phy>; 233 phy-names = "pcie"; 234 status = "disabled"; 235 }; 236 237 usb: usb@ffe09080 { 238 compatible = "amlogic,meson-axg-usb-ctrl"; 239 reg = <0x0 0xffe09080 0x0 0x20>; 240 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 241 #address-cells = <2>; 242 #size-cells = <2>; 243 ranges; 244 245 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; 246 clock-names = "usb_ctrl", "ddr"; 247 resets = <&reset RESET_USB_OTG>; 248 249 dr_mode = "otg"; 250 251 phys = <&usb2_phy1>; 252 phy-names = "usb2-phy1"; 253 254 dwc2: usb@ff400000 { 255 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 256 reg = <0x0 0xff400000 0x0 0x40000>; 257 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&clkc CLKID_USB1>; 259 clock-names = "otg"; 260 phys = <&usb2_phy1>; 261 dr_mode = "peripheral"; 262 g-rx-fifo-size = <192>; 263 g-np-tx-fifo-size = <128>; 264 g-tx-fifo-size = <128 128 16 16 16>; 265 }; 266 267 dwc3: usb@ff500000 { 268 compatible = "snps,dwc3"; 269 reg = <0x0 0xff500000 0x0 0x100000>; 270 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 271 dr_mode = "host"; 272 maximum-speed = "high-speed"; 273 snps,dis_u2_susphy_quirk; 274 }; 275 }; 276 277 ethmac: ethernet@ff3f0000 { 278 compatible = "amlogic,meson-axg-dwmac", 279 "snps,dwmac-3.70a", 280 "snps,dwmac"; 281 reg = <0x0 0xff3f0000 0x0 0x10000>, 282 <0x0 0xff634540 0x0 0x8>; 283 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 284 interrupt-names = "macirq"; 285 clocks = <&clkc CLKID_ETH>, 286 <&clkc CLKID_FCLK_DIV2>, 287 <&clkc CLKID_MPLL2>, 288 <&clkc CLKID_FCLK_DIV2>; 289 clock-names = "stmmaceth", "clkin0", "clkin1", 290 "timing-adjustment"; 291 rx-fifo-depth = <4096>; 292 tx-fifo-depth = <2048>; 293 power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>; 294 status = "disabled"; 295 }; 296 297 pcie_phy: phy@ff644000 { 298 compatible = "amlogic,axg-pcie-phy"; 299 reg = <0x0 0xff644000 0x0 0x1c>; 300 resets = <&reset RESET_PCIE_PHY>; 301 phys = <&mipi_pcie_analog_dphy>; 302 phy-names = "analog"; 303 #phy-cells = <0>; 304 }; 305 306 pdm: audio-controller@ff632000 { 307 compatible = "amlogic,axg-pdm"; 308 reg = <0x0 0xff632000 0x0 0x34>; 309 #sound-dai-cells = <0>; 310 sound-name-prefix = "PDM"; 311 clocks = <&clkc_audio AUD_CLKID_PDM>, 312 <&clkc_audio AUD_CLKID_PDM_DCLK>, 313 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 314 clock-names = "pclk", "dclk", "sysclk"; 315 status = "disabled"; 316 }; 317 318 periphs: bus@ff634000 { 319 compatible = "simple-bus"; 320 reg = <0x0 0xff634000 0x0 0x2000>; 321 #address-cells = <2>; 322 #size-cells = <2>; 323 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 324 325 hwrng: rng@18 { 326 compatible = "amlogic,meson-rng"; 327 reg = <0x0 0x18 0x0 0x4>; 328 clocks = <&clkc CLKID_RNG0>; 329 clock-names = "core"; 330 }; 331 332 pinctrl_periphs: pinctrl@480 { 333 compatible = "amlogic,meson-axg-periphs-pinctrl"; 334 #address-cells = <2>; 335 #size-cells = <2>; 336 ranges; 337 338 gpio: bank@480 { 339 reg = <0x0 0x00480 0x0 0x40>, 340 <0x0 0x004e8 0x0 0x14>, 341 <0x0 0x00520 0x0 0x14>, 342 <0x0 0x00430 0x0 0x3c>; 343 reg-names = "mux", "pull", "pull-enable", "gpio"; 344 gpio-controller; 345 #gpio-cells = <2>; 346 gpio-ranges = <&pinctrl_periphs 0 0 86>; 347 }; 348 349 i2c0_pins: i2c0 { 350 mux { 351 groups = "i2c0_sck", 352 "i2c0_sda"; 353 function = "i2c0"; 354 bias-disable; 355 }; 356 }; 357 358 i2c1_x_pins: i2c1_x { 359 mux { 360 groups = "i2c1_sck_x", 361 "i2c1_sda_x"; 362 function = "i2c1"; 363 bias-disable; 364 }; 365 }; 366 367 i2c1_z_pins: i2c1_z { 368 mux { 369 groups = "i2c1_sck_z", 370 "i2c1_sda_z"; 371 function = "i2c1"; 372 bias-disable; 373 }; 374 }; 375 376 i2c2_a_pins: i2c2_a { 377 mux { 378 groups = "i2c2_sck_a", 379 "i2c2_sda_a"; 380 function = "i2c2"; 381 bias-disable; 382 }; 383 }; 384 385 i2c2_x_pins: i2c2_x { 386 mux { 387 groups = "i2c2_sck_x", 388 "i2c2_sda_x"; 389 function = "i2c2"; 390 bias-disable; 391 }; 392 }; 393 394 i2c3_a6_pins: i2c3_a6 { 395 mux { 396 groups = "i2c3_sda_a6", 397 "i2c3_sck_a7"; 398 function = "i2c3"; 399 bias-disable; 400 }; 401 }; 402 403 i2c3_a12_pins: i2c3_a12 { 404 mux { 405 groups = "i2c3_sda_a12", 406 "i2c3_sck_a13"; 407 function = "i2c3"; 408 bias-disable; 409 }; 410 }; 411 412 i2c3_a19_pins: i2c3_a19 { 413 mux { 414 groups = "i2c3_sda_a19", 415 "i2c3_sck_a20"; 416 function = "i2c3"; 417 bias-disable; 418 }; 419 }; 420 421 emmc_pins: emmc { 422 mux-0 { 423 groups = "emmc_nand_d0", 424 "emmc_nand_d1", 425 "emmc_nand_d2", 426 "emmc_nand_d3", 427 "emmc_nand_d4", 428 "emmc_nand_d5", 429 "emmc_nand_d6", 430 "emmc_nand_d7", 431 "emmc_cmd"; 432 function = "emmc"; 433 bias-pull-up; 434 }; 435 436 mux-1 { 437 groups = "emmc_clk"; 438 function = "emmc"; 439 bias-disable; 440 }; 441 }; 442 443 nand_all_pins: nand-all-pins { 444 mux { 445 groups = "emmc_nand_d0", 446 "emmc_nand_d1", 447 "emmc_nand_d2", 448 "emmc_nand_d3", 449 "emmc_nand_d4", 450 "emmc_nand_d5", 451 "emmc_nand_d6", 452 "emmc_nand_d7", 453 "nand_ce0", 454 "nand_ale", 455 "nand_cle", 456 "nand_wen_clk", 457 "nand_ren_wr"; 458 function = "nand"; 459 input-enable; 460 bias-pull-up; 461 }; 462 }; 463 464 emmc_ds_pins: emmc_ds { 465 mux { 466 groups = "emmc_ds"; 467 function = "emmc"; 468 bias-pull-down; 469 }; 470 }; 471 472 emmc_clk_gate_pins: emmc_clk_gate { 473 mux { 474 groups = "BOOT_8"; 475 function = "gpio_periphs"; 476 bias-pull-down; 477 }; 478 }; 479 480 eth_rgmii_x_pins: eth-x-rgmii { 481 mux { 482 groups = "eth_mdio_x", 483 "eth_mdc_x", 484 "eth_rgmii_rx_clk_x", 485 "eth_rx_dv_x", 486 "eth_rxd0_x", 487 "eth_rxd1_x", 488 "eth_rxd2_rgmii", 489 "eth_rxd3_rgmii", 490 "eth_rgmii_tx_clk", 491 "eth_txen_x", 492 "eth_txd0_x", 493 "eth_txd1_x", 494 "eth_txd2_rgmii", 495 "eth_txd3_rgmii"; 496 function = "eth"; 497 bias-disable; 498 }; 499 }; 500 501 eth_rgmii_y_pins: eth-y-rgmii { 502 mux { 503 groups = "eth_mdio_y", 504 "eth_mdc_y", 505 "eth_rgmii_rx_clk_y", 506 "eth_rx_dv_y", 507 "eth_rxd0_y", 508 "eth_rxd1_y", 509 "eth_rxd2_rgmii", 510 "eth_rxd3_rgmii", 511 "eth_rgmii_tx_clk", 512 "eth_txen_y", 513 "eth_txd0_y", 514 "eth_txd1_y", 515 "eth_txd2_rgmii", 516 "eth_txd3_rgmii"; 517 function = "eth"; 518 bias-disable; 519 }; 520 }; 521 522 eth_rmii_x_pins: eth-x-rmii { 523 mux { 524 groups = "eth_mdio_x", 525 "eth_mdc_x", 526 "eth_rgmii_rx_clk_x", 527 "eth_rx_dv_x", 528 "eth_rxd0_x", 529 "eth_rxd1_x", 530 "eth_txen_x", 531 "eth_txd0_x", 532 "eth_txd1_x"; 533 function = "eth"; 534 bias-disable; 535 }; 536 }; 537 538 eth_rmii_y_pins: eth-y-rmii { 539 mux { 540 groups = "eth_mdio_y", 541 "eth_mdc_y", 542 "eth_rgmii_rx_clk_y", 543 "eth_rx_dv_y", 544 "eth_rxd0_y", 545 "eth_rxd1_y", 546 "eth_txen_y", 547 "eth_txd0_y", 548 "eth_txd1_y"; 549 function = "eth"; 550 bias-disable; 551 }; 552 }; 553 554 mclk_b_pins: mclk_b { 555 mux { 556 groups = "mclk_b"; 557 function = "mclk_b"; 558 bias-disable; 559 }; 560 }; 561 562 mclk_c_pins: mclk_c { 563 mux { 564 groups = "mclk_c"; 565 function = "mclk_c"; 566 bias-disable; 567 }; 568 }; 569 570 pdm_dclk_a14_pins: pdm_dclk_a14 { 571 mux { 572 groups = "pdm_dclk_a14"; 573 function = "pdm"; 574 bias-disable; 575 }; 576 }; 577 578 pdm_dclk_a19_pins: pdm_dclk_a19 { 579 mux { 580 groups = "pdm_dclk_a19"; 581 function = "pdm"; 582 bias-disable; 583 }; 584 }; 585 586 pdm_din0_pins: pdm_din0 { 587 mux { 588 groups = "pdm_din0"; 589 function = "pdm"; 590 bias-disable; 591 }; 592 }; 593 594 pdm_din1_pins: pdm_din1 { 595 mux { 596 groups = "pdm_din1"; 597 function = "pdm"; 598 bias-disable; 599 }; 600 }; 601 602 pdm_din2_pins: pdm_din2 { 603 mux { 604 groups = "pdm_din2"; 605 function = "pdm"; 606 bias-disable; 607 }; 608 }; 609 610 pdm_din3_pins: pdm_din3 { 611 mux { 612 groups = "pdm_din3"; 613 function = "pdm"; 614 bias-disable; 615 }; 616 }; 617 618 pwm_a_a_pins: pwm_a_a { 619 mux { 620 groups = "pwm_a_a"; 621 function = "pwm_a"; 622 bias-disable; 623 }; 624 }; 625 626 pwm_a_x18_pins: pwm_a_x18 { 627 mux { 628 groups = "pwm_a_x18"; 629 function = "pwm_a"; 630 bias-disable; 631 }; 632 }; 633 634 pwm_a_x20_pins: pwm_a_x20 { 635 mux { 636 groups = "pwm_a_x20"; 637 function = "pwm_a"; 638 bias-disable; 639 }; 640 }; 641 642 pwm_a_z_pins: pwm_a_z { 643 mux { 644 groups = "pwm_a_z"; 645 function = "pwm_a"; 646 bias-disable; 647 }; 648 }; 649 650 pwm_b_a_pins: pwm_b_a { 651 mux { 652 groups = "pwm_b_a"; 653 function = "pwm_b"; 654 bias-disable; 655 }; 656 }; 657 658 pwm_b_x_pins: pwm_b_x { 659 mux { 660 groups = "pwm_b_x"; 661 function = "pwm_b"; 662 bias-disable; 663 }; 664 }; 665 666 pwm_b_z_pins: pwm_b_z { 667 mux { 668 groups = "pwm_b_z"; 669 function = "pwm_b"; 670 bias-disable; 671 }; 672 }; 673 674 pwm_c_a_pins: pwm_c_a { 675 mux { 676 groups = "pwm_c_a"; 677 function = "pwm_c"; 678 bias-disable; 679 }; 680 }; 681 682 pwm_c_x10_pins: pwm_c_x10 { 683 mux { 684 groups = "pwm_c_x10"; 685 function = "pwm_c"; 686 bias-disable; 687 }; 688 }; 689 690 pwm_c_x17_pins: pwm_c_x17 { 691 mux { 692 groups = "pwm_c_x17"; 693 function = "pwm_c"; 694 bias-disable; 695 }; 696 }; 697 698 pwm_d_x11_pins: pwm_d_x11 { 699 mux { 700 groups = "pwm_d_x11"; 701 function = "pwm_d"; 702 bias-disable; 703 }; 704 }; 705 706 pwm_d_x16_pins: pwm_d_x16 { 707 mux { 708 groups = "pwm_d_x16"; 709 function = "pwm_d"; 710 bias-disable; 711 }; 712 }; 713 714 sdio_pins: sdio { 715 mux-0 { 716 groups = "sdio_d0", 717 "sdio_d1", 718 "sdio_d2", 719 "sdio_d3", 720 "sdio_cmd"; 721 function = "sdio"; 722 bias-pull-up; 723 }; 724 725 mux-1 { 726 groups = "sdio_clk"; 727 function = "sdio"; 728 bias-disable; 729 }; 730 }; 731 732 sdio_clk_gate_pins: sdio_clk_gate { 733 mux { 734 groups = "GPIOX_4"; 735 function = "gpio_periphs"; 736 bias-pull-down; 737 }; 738 }; 739 740 spdif_in_z_pins: spdif_in_z { 741 mux { 742 groups = "spdif_in_z"; 743 function = "spdif_in"; 744 bias-disable; 745 }; 746 }; 747 748 spdif_in_a1_pins: spdif_in_a1 { 749 mux { 750 groups = "spdif_in_a1"; 751 function = "spdif_in"; 752 bias-disable; 753 }; 754 }; 755 756 spdif_in_a7_pins: spdif_in_a7 { 757 mux { 758 groups = "spdif_in_a7"; 759 function = "spdif_in"; 760 bias-disable; 761 }; 762 }; 763 764 spdif_in_a19_pins: spdif_in_a19 { 765 mux { 766 groups = "spdif_in_a19"; 767 function = "spdif_in"; 768 bias-disable; 769 }; 770 }; 771 772 spdif_in_a20_pins: spdif_in_a20 { 773 mux { 774 groups = "spdif_in_a20"; 775 function = "spdif_in"; 776 bias-disable; 777 }; 778 }; 779 780 spdif_out_a1_pins: spdif_out_a1 { 781 mux { 782 groups = "spdif_out_a1"; 783 function = "spdif_out"; 784 bias-disable; 785 }; 786 }; 787 788 spdif_out_a11_pins: spdif_out_a11 { 789 mux { 790 groups = "spdif_out_a11"; 791 function = "spdif_out"; 792 bias-disable; 793 }; 794 }; 795 796 spdif_out_a19_pins: spdif_out_a19 { 797 mux { 798 groups = "spdif_out_a19"; 799 function = "spdif_out"; 800 bias-disable; 801 }; 802 }; 803 804 spdif_out_a20_pins: spdif_out_a20 { 805 mux { 806 groups = "spdif_out_a20"; 807 function = "spdif_out"; 808 bias-disable; 809 }; 810 }; 811 812 spdif_out_z_pins: spdif_out_z { 813 mux { 814 groups = "spdif_out_z"; 815 function = "spdif_out"; 816 bias-disable; 817 }; 818 }; 819 820 spi0_pins: spi0 { 821 mux { 822 groups = "spi0_miso", 823 "spi0_mosi", 824 "spi0_clk"; 825 function = "spi0"; 826 bias-disable; 827 }; 828 }; 829 830 spi0_ss0_pins: spi0_ss0 { 831 mux { 832 groups = "spi0_ss0"; 833 function = "spi0"; 834 bias-disable; 835 }; 836 }; 837 838 spi0_ss1_pins: spi0_ss1 { 839 mux { 840 groups = "spi0_ss1"; 841 function = "spi0"; 842 bias-disable; 843 }; 844 }; 845 846 spi0_ss2_pins: spi0_ss2 { 847 mux { 848 groups = "spi0_ss2"; 849 function = "spi0"; 850 bias-disable; 851 }; 852 }; 853 854 spi1_a_pins: spi1_a { 855 mux { 856 groups = "spi1_miso_a", 857 "spi1_mosi_a", 858 "spi1_clk_a"; 859 function = "spi1"; 860 bias-disable; 861 }; 862 }; 863 864 spi1_ss0_a_pins: spi1_ss0_a { 865 mux { 866 groups = "spi1_ss0_a"; 867 function = "spi1"; 868 bias-disable; 869 }; 870 }; 871 872 spi1_ss1_pins: spi1_ss1 { 873 mux { 874 groups = "spi1_ss1"; 875 function = "spi1"; 876 bias-disable; 877 }; 878 }; 879 880 spi1_x_pins: spi1_x { 881 mux { 882 groups = "spi1_miso_x", 883 "spi1_mosi_x", 884 "spi1_clk_x"; 885 function = "spi1"; 886 bias-disable; 887 }; 888 }; 889 890 spi1_ss0_x_pins: spi1_ss0_x { 891 mux { 892 groups = "spi1_ss0_x"; 893 function = "spi1"; 894 bias-disable; 895 }; 896 }; 897 898 tdma_din0_pins: tdma_din0 { 899 mux { 900 groups = "tdma_din0"; 901 function = "tdma"; 902 bias-disable; 903 }; 904 }; 905 906 tdma_dout0_x14_pins: tdma_dout0_x14 { 907 mux { 908 groups = "tdma_dout0_x14"; 909 function = "tdma"; 910 bias-disable; 911 }; 912 }; 913 914 tdma_dout0_x15_pins: tdma_dout0_x15 { 915 mux { 916 groups = "tdma_dout0_x15"; 917 function = "tdma"; 918 bias-disable; 919 }; 920 }; 921 922 tdma_dout1_pins: tdma_dout1 { 923 mux { 924 groups = "tdma_dout1"; 925 function = "tdma"; 926 bias-disable; 927 }; 928 }; 929 930 tdma_din1_pins: tdma_din1 { 931 mux { 932 groups = "tdma_din1"; 933 function = "tdma"; 934 bias-disable; 935 }; 936 }; 937 938 tdma_fs_pins: tdma_fs { 939 mux { 940 groups = "tdma_fs"; 941 function = "tdma"; 942 bias-disable; 943 }; 944 }; 945 946 tdma_fs_slv_pins: tdma_fs_slv { 947 mux { 948 groups = "tdma_fs_slv"; 949 function = "tdma"; 950 bias-disable; 951 }; 952 }; 953 954 tdma_sclk_pins: tdma_sclk { 955 mux { 956 groups = "tdma_sclk"; 957 function = "tdma"; 958 bias-disable; 959 }; 960 }; 961 962 tdma_sclk_slv_pins: tdma_sclk_slv { 963 mux { 964 groups = "tdma_sclk_slv"; 965 function = "tdma"; 966 bias-disable; 967 }; 968 }; 969 970 tdmb_din0_pins: tdmb_din0 { 971 mux { 972 groups = "tdmb_din0"; 973 function = "tdmb"; 974 bias-disable; 975 }; 976 }; 977 978 tdmb_din1_pins: tdmb_din1 { 979 mux { 980 groups = "tdmb_din1"; 981 function = "tdmb"; 982 bias-disable; 983 }; 984 }; 985 986 tdmb_din2_pins: tdmb_din2 { 987 mux { 988 groups = "tdmb_din2"; 989 function = "tdmb"; 990 bias-disable; 991 }; 992 }; 993 994 tdmb_din3_pins: tdmb_din3 { 995 mux { 996 groups = "tdmb_din3"; 997 function = "tdmb"; 998 bias-disable; 999 }; 1000 }; 1001 1002 tdmb_dout0_pins: tdmb_dout0 { 1003 mux { 1004 groups = "tdmb_dout0"; 1005 function = "tdmb"; 1006 bias-disable; 1007 }; 1008 }; 1009 1010 tdmb_dout1_pins: tdmb_dout1 { 1011 mux { 1012 groups = "tdmb_dout1"; 1013 function = "tdmb"; 1014 bias-disable; 1015 }; 1016 }; 1017 1018 tdmb_dout2_pins: tdmb_dout2 { 1019 mux { 1020 groups = "tdmb_dout2"; 1021 function = "tdmb"; 1022 bias-disable; 1023 }; 1024 }; 1025 1026 tdmb_dout3_pins: tdmb_dout3 { 1027 mux { 1028 groups = "tdmb_dout3"; 1029 function = "tdmb"; 1030 bias-disable; 1031 }; 1032 }; 1033 1034 tdmb_fs_pins: tdmb_fs { 1035 mux { 1036 groups = "tdmb_fs"; 1037 function = "tdmb"; 1038 bias-disable; 1039 }; 1040 }; 1041 1042 tdmb_fs_slv_pins: tdmb_fs_slv { 1043 mux { 1044 groups = "tdmb_fs_slv"; 1045 function = "tdmb"; 1046 bias-disable; 1047 }; 1048 }; 1049 1050 tdmb_sclk_pins: tdmb_sclk { 1051 mux { 1052 groups = "tdmb_sclk"; 1053 function = "tdmb"; 1054 bias-disable; 1055 }; 1056 }; 1057 1058 tdmb_sclk_slv_pins: tdmb_sclk_slv { 1059 mux { 1060 groups = "tdmb_sclk_slv"; 1061 function = "tdmb"; 1062 bias-disable; 1063 }; 1064 }; 1065 1066 tdmc_fs_pins: tdmc_fs { 1067 mux { 1068 groups = "tdmc_fs"; 1069 function = "tdmc"; 1070 bias-disable; 1071 }; 1072 }; 1073 1074 tdmc_fs_slv_pins: tdmc_fs_slv { 1075 mux { 1076 groups = "tdmc_fs_slv"; 1077 function = "tdmc"; 1078 bias-disable; 1079 }; 1080 }; 1081 1082 tdmc_sclk_pins: tdmc_sclk { 1083 mux { 1084 groups = "tdmc_sclk"; 1085 function = "tdmc"; 1086 bias-disable; 1087 }; 1088 }; 1089 1090 tdmc_sclk_slv_pins: tdmc_sclk_slv { 1091 mux { 1092 groups = "tdmc_sclk_slv"; 1093 function = "tdmc"; 1094 bias-disable; 1095 }; 1096 }; 1097 1098 tdmc_din0_pins: tdmc_din0 { 1099 mux { 1100 groups = "tdmc_din0"; 1101 function = "tdmc"; 1102 bias-disable; 1103 }; 1104 }; 1105 1106 tdmc_din1_pins: tdmc_din1 { 1107 mux { 1108 groups = "tdmc_din1"; 1109 function = "tdmc"; 1110 bias-disable; 1111 }; 1112 }; 1113 1114 tdmc_din2_pins: tdmc_din2 { 1115 mux { 1116 groups = "tdmc_din2"; 1117 function = "tdmc"; 1118 bias-disable; 1119 }; 1120 }; 1121 1122 tdmc_din3_pins: tdmc_din3 { 1123 mux { 1124 groups = "tdmc_din3"; 1125 function = "tdmc"; 1126 bias-disable; 1127 }; 1128 }; 1129 1130 tdmc_dout0_pins: tdmc_dout0 { 1131 mux { 1132 groups = "tdmc_dout0"; 1133 function = "tdmc"; 1134 bias-disable; 1135 }; 1136 }; 1137 1138 tdmc_dout1_pins: tdmc_dout1 { 1139 mux { 1140 groups = "tdmc_dout1"; 1141 function = "tdmc"; 1142 bias-disable; 1143 }; 1144 }; 1145 1146 tdmc_dout2_pins: tdmc_dout2 { 1147 mux { 1148 groups = "tdmc_dout2"; 1149 function = "tdmc"; 1150 bias-disable; 1151 }; 1152 }; 1153 1154 tdmc_dout3_pins: tdmc_dout3 { 1155 mux { 1156 groups = "tdmc_dout3"; 1157 function = "tdmc"; 1158 bias-disable; 1159 }; 1160 }; 1161 1162 uart_a_pins: uart_a { 1163 mux { 1164 groups = "uart_tx_a", 1165 "uart_rx_a"; 1166 function = "uart_a"; 1167 bias-disable; 1168 }; 1169 }; 1170 1171 uart_a_cts_rts_pins: uart_a_cts_rts { 1172 mux { 1173 groups = "uart_cts_a", 1174 "uart_rts_a"; 1175 function = "uart_a"; 1176 bias-disable; 1177 }; 1178 }; 1179 1180 uart_b_x_pins: uart_b_x { 1181 mux { 1182 groups = "uart_tx_b_x", 1183 "uart_rx_b_x"; 1184 function = "uart_b"; 1185 bias-disable; 1186 }; 1187 }; 1188 1189 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 1190 mux { 1191 groups = "uart_cts_b_x", 1192 "uart_rts_b_x"; 1193 function = "uart_b"; 1194 bias-disable; 1195 }; 1196 }; 1197 1198 uart_b_z_pins: uart_b_z { 1199 mux { 1200 groups = "uart_tx_b_z", 1201 "uart_rx_b_z"; 1202 function = "uart_b"; 1203 bias-disable; 1204 }; 1205 }; 1206 1207 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 1208 mux { 1209 groups = "uart_cts_b_z", 1210 "uart_rts_b_z"; 1211 function = "uart_b"; 1212 bias-disable; 1213 }; 1214 }; 1215 1216 uart_ao_b_z_pins: uart_ao_b_z { 1217 mux { 1218 groups = "uart_ao_tx_b_z", 1219 "uart_ao_rx_b_z"; 1220 function = "uart_ao_b_z"; 1221 bias-disable; 1222 }; 1223 }; 1224 1225 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 1226 mux { 1227 groups = "uart_ao_cts_b_z", 1228 "uart_ao_rts_b_z"; 1229 function = "uart_ao_b_z"; 1230 bias-disable; 1231 }; 1232 }; 1233 }; 1234 }; 1235 1236 hiubus: bus@ff63c000 { 1237 compatible = "simple-bus"; 1238 reg = <0x0 0xff63c000 0x0 0x1c00>; 1239 #address-cells = <2>; 1240 #size-cells = <2>; 1241 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 1242 1243 sysctrl: system-controller@0 { 1244 compatible = "amlogic,meson-axg-hhi-sysctrl", 1245 "simple-mfd", "syscon"; 1246 reg = <0 0 0 0x400>; 1247 1248 clkc: clock-controller { 1249 compatible = "amlogic,axg-clkc"; 1250 #clock-cells = <1>; 1251 clocks = <&xtal>; 1252 clock-names = "xtal"; 1253 }; 1254 1255 pwrc: power-controller { 1256 compatible = "amlogic,meson-axg-pwrc"; 1257 #power-domain-cells = <1>; 1258 amlogic,ao-sysctrl = <&sysctrl_AO>; 1259 resets = <&reset RESET_VIU>, 1260 <&reset RESET_VENC>, 1261 <&reset RESET_VCBUS>, 1262 <&reset RESET_VENCL>, 1263 <&reset RESET_VID_LOCK>; 1264 reset-names = "viu", "venc", "vcbus", 1265 "vencl", "vid_lock"; 1266 clocks = <&clkc CLKID_VPU>, 1267 <&clkc CLKID_VAPB>; 1268 clock-names = "vpu", "vapb"; 1269 /* 1270 * VPU clocking is provided by two identical clock paths 1271 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1272 * free mux to safely change frequency while running. 1273 * Same for VAPB but with a final gate after the glitch free mux. 1274 */ 1275 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1276 <&clkc CLKID_VPU_0>, 1277 <&clkc CLKID_VPU>, /* Glitch free mux */ 1278 <&clkc CLKID_VAPB_0_SEL>, 1279 <&clkc CLKID_VAPB_0>, 1280 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1281 assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>, 1282 <0>, /* Do Nothing */ 1283 <&clkc CLKID_VPU_0>, 1284 <&clkc CLKID_FCLK_DIV4>, 1285 <0>, /* Do Nothing */ 1286 <&clkc CLKID_VAPB_0>; 1287 assigned-clock-rates = <0>, /* Do Nothing */ 1288 <250000000>, 1289 <0>, /* Do Nothing */ 1290 <0>, /* Do Nothing */ 1291 <250000000>, 1292 <0>; /* Do Nothing */ 1293 }; 1294 1295 mipi_pcie_analog_dphy: phy { 1296 compatible = "amlogic,axg-mipi-pcie-analog-phy"; 1297 #phy-cells = <0>; 1298 status = "disabled"; 1299 }; 1300 }; 1301 }; 1302 1303 mailbox: mailbox@ff63c404 { 1304 compatible = "amlogic,meson-gxbb-mhu"; 1305 reg = <0 0xff63c404 0 0x4c>; 1306 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 1307 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 1308 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 1309 #mbox-cells = <1>; 1310 }; 1311 1312 mipi_dphy: phy@ff640000 { 1313 compatible = "amlogic,axg-mipi-dphy"; 1314 reg = <0x0 0xff640000 0x0 0x100>; 1315 clocks = <&clkc CLKID_MIPI_DSI_PHY>; 1316 clock-names = "pclk"; 1317 resets = <&reset RESET_MIPI_PHY>; 1318 reset-names = "phy"; 1319 phys = <&mipi_pcie_analog_dphy>; 1320 phy-names = "analog"; 1321 #phy-cells = <0>; 1322 status = "disabled"; 1323 }; 1324 1325 audio: bus@ff642000 { 1326 compatible = "simple-bus"; 1327 reg = <0x0 0xff642000 0x0 0x2000>; 1328 #address-cells = <2>; 1329 #size-cells = <2>; 1330 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 1331 1332 clkc_audio: clock-controller@0 { 1333 compatible = "amlogic,axg-audio-clkc"; 1334 reg = <0x0 0x0 0x0 0xb4>; 1335 #clock-cells = <1>; 1336 1337 clocks = <&clkc CLKID_AUDIO>, 1338 <&clkc CLKID_MPLL0>, 1339 <&clkc CLKID_MPLL1>, 1340 <&clkc CLKID_MPLL2>, 1341 <&clkc CLKID_MPLL3>, 1342 <&clkc CLKID_HIFI_PLL>, 1343 <&clkc CLKID_FCLK_DIV3>, 1344 <&clkc CLKID_FCLK_DIV4>, 1345 <&clkc CLKID_GP0_PLL>; 1346 clock-names = "pclk", 1347 "mst_in0", 1348 "mst_in1", 1349 "mst_in2", 1350 "mst_in3", 1351 "mst_in4", 1352 "mst_in5", 1353 "mst_in6", 1354 "mst_in7"; 1355 1356 resets = <&reset RESET_AUDIO>; 1357 }; 1358 1359 toddr_a: audio-controller@100 { 1360 compatible = "amlogic,axg-toddr"; 1361 reg = <0x0 0x100 0x0 0x2c>; 1362 #sound-dai-cells = <0>; 1363 sound-name-prefix = "TODDR_A"; 1364 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 1365 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1366 resets = <&arb AXG_ARB_TODDR_A>; 1367 amlogic,fifo-depth = <512>; 1368 status = "disabled"; 1369 }; 1370 1371 toddr_b: audio-controller@140 { 1372 compatible = "amlogic,axg-toddr"; 1373 reg = <0x0 0x140 0x0 0x2c>; 1374 #sound-dai-cells = <0>; 1375 sound-name-prefix = "TODDR_B"; 1376 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1377 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1378 resets = <&arb AXG_ARB_TODDR_B>; 1379 amlogic,fifo-depth = <256>; 1380 status = "disabled"; 1381 }; 1382 1383 toddr_c: audio-controller@180 { 1384 compatible = "amlogic,axg-toddr"; 1385 reg = <0x0 0x180 0x0 0x2c>; 1386 #sound-dai-cells = <0>; 1387 sound-name-prefix = "TODDR_C"; 1388 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; 1389 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1390 resets = <&arb AXG_ARB_TODDR_C>; 1391 amlogic,fifo-depth = <256>; 1392 status = "disabled"; 1393 }; 1394 1395 frddr_a: audio-controller@1c0 { 1396 compatible = "amlogic,axg-frddr"; 1397 reg = <0x0 0x1c0 0x0 0x2c>; 1398 #sound-dai-cells = <0>; 1399 sound-name-prefix = "FRDDR_A"; 1400 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 1401 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1402 resets = <&arb AXG_ARB_FRDDR_A>; 1403 amlogic,fifo-depth = <512>; 1404 status = "disabled"; 1405 }; 1406 1407 frddr_b: audio-controller@200 { 1408 compatible = "amlogic,axg-frddr"; 1409 reg = <0x0 0x200 0x0 0x2c>; 1410 #sound-dai-cells = <0>; 1411 sound-name-prefix = "FRDDR_B"; 1412 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 1413 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1414 resets = <&arb AXG_ARB_FRDDR_B>; 1415 amlogic,fifo-depth = <256>; 1416 status = "disabled"; 1417 }; 1418 1419 frddr_c: audio-controller@240 { 1420 compatible = "amlogic,axg-frddr"; 1421 reg = <0x0 0x240 0x0 0x2c>; 1422 #sound-dai-cells = <0>; 1423 sound-name-prefix = "FRDDR_C"; 1424 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 1425 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1426 resets = <&arb AXG_ARB_FRDDR_C>; 1427 amlogic,fifo-depth = <256>; 1428 status = "disabled"; 1429 }; 1430 1431 arb: reset-controller@280 { 1432 compatible = "amlogic,meson-axg-audio-arb"; 1433 reg = <0x0 0x280 0x0 0x4>; 1434 #reset-cells = <1>; 1435 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1436 }; 1437 1438 tdmin_a: audio-controller@300 { 1439 compatible = "amlogic,axg-tdmin"; 1440 reg = <0x0 0x300 0x0 0x40>; 1441 sound-name-prefix = "TDMIN_A"; 1442 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1443 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1444 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1445 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1446 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1447 clock-names = "pclk", "sclk", "sclk_sel", 1448 "lrclk", "lrclk_sel"; 1449 status = "disabled"; 1450 }; 1451 1452 tdmin_b: audio-controller@340 { 1453 compatible = "amlogic,axg-tdmin"; 1454 reg = <0x0 0x340 0x0 0x40>; 1455 sound-name-prefix = "TDMIN_B"; 1456 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1457 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1458 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1459 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1460 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1461 clock-names = "pclk", "sclk", "sclk_sel", 1462 "lrclk", "lrclk_sel"; 1463 status = "disabled"; 1464 }; 1465 1466 tdmin_c: audio-controller@380 { 1467 compatible = "amlogic,axg-tdmin"; 1468 reg = <0x0 0x380 0x0 0x40>; 1469 sound-name-prefix = "TDMIN_C"; 1470 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1471 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1472 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1473 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1474 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1475 clock-names = "pclk", "sclk", "sclk_sel", 1476 "lrclk", "lrclk_sel"; 1477 status = "disabled"; 1478 }; 1479 1480 tdmin_lb: audio-controller@3c0 { 1481 compatible = "amlogic,axg-tdmin"; 1482 reg = <0x0 0x3c0 0x0 0x40>; 1483 sound-name-prefix = "TDMIN_LB"; 1484 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1485 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1486 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1487 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1488 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1489 clock-names = "pclk", "sclk", "sclk_sel", 1490 "lrclk", "lrclk_sel"; 1491 status = "disabled"; 1492 }; 1493 1494 spdifin: audio-controller@400 { 1495 compatible = "amlogic,axg-spdifin"; 1496 reg = <0x0 0x400 0x0 0x30>; 1497 #sound-dai-cells = <0>; 1498 sound-name-prefix = "SPDIFIN"; 1499 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; 1500 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1501 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1502 clock-names = "pclk", "refclk"; 1503 status = "disabled"; 1504 }; 1505 1506 spdifout: audio-controller@480 { 1507 compatible = "amlogic,axg-spdifout"; 1508 reg = <0x0 0x480 0x0 0x50>; 1509 #sound-dai-cells = <0>; 1510 sound-name-prefix = "SPDIFOUT"; 1511 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1512 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1513 clock-names = "pclk", "mclk"; 1514 status = "disabled"; 1515 }; 1516 1517 tdmout_a: audio-controller@500 { 1518 compatible = "amlogic,axg-tdmout"; 1519 reg = <0x0 0x500 0x0 0x40>; 1520 sound-name-prefix = "TDMOUT_A"; 1521 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1522 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1523 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1524 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1525 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1526 clock-names = "pclk", "sclk", "sclk_sel", 1527 "lrclk", "lrclk_sel"; 1528 status = "disabled"; 1529 }; 1530 1531 tdmout_b: audio-controller@540 { 1532 compatible = "amlogic,axg-tdmout"; 1533 reg = <0x0 0x540 0x0 0x40>; 1534 sound-name-prefix = "TDMOUT_B"; 1535 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1536 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1537 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1538 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1539 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1540 clock-names = "pclk", "sclk", "sclk_sel", 1541 "lrclk", "lrclk_sel"; 1542 status = "disabled"; 1543 }; 1544 1545 tdmout_c: audio-controller@580 { 1546 compatible = "amlogic,axg-tdmout"; 1547 reg = <0x0 0x580 0x0 0x40>; 1548 sound-name-prefix = "TDMOUT_C"; 1549 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1550 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1551 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1552 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1553 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1554 clock-names = "pclk", "sclk", "sclk_sel", 1555 "lrclk", "lrclk_sel"; 1556 status = "disabled"; 1557 }; 1558 }; 1559 1560 aobus: bus@ff800000 { 1561 compatible = "simple-bus"; 1562 reg = <0x0 0xff800000 0x0 0x100000>; 1563 #address-cells = <2>; 1564 #size-cells = <2>; 1565 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1566 1567 sysctrl_AO: sys-ctrl@0 { 1568 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; 1569 reg = <0x0 0x0 0x0 0x100>; 1570 1571 clkc_AO: clock-controller { 1572 compatible = "amlogic,meson-axg-aoclkc"; 1573 #clock-cells = <1>; 1574 #reset-cells = <1>; 1575 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1576 clock-names = "xtal", "mpeg-clk"; 1577 }; 1578 }; 1579 1580 pinctrl_aobus: pinctrl@14 { 1581 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1582 #address-cells = <2>; 1583 #size-cells = <2>; 1584 ranges; 1585 1586 gpio_ao: bank@14 { 1587 reg = <0x0 0x00014 0x0 0x8>, 1588 <0x0 0x0002c 0x0 0x4>, 1589 <0x0 0x00024 0x0 0x8>; 1590 reg-names = "mux", "pull", "gpio"; 1591 gpio-controller; 1592 #gpio-cells = <2>; 1593 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1594 }; 1595 1596 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1597 mux { 1598 groups = "i2c_ao_sck_4"; 1599 function = "i2c_ao"; 1600 bias-disable; 1601 }; 1602 }; 1603 1604 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1605 mux { 1606 groups = "i2c_ao_sck_8"; 1607 function = "i2c_ao"; 1608 bias-disable; 1609 }; 1610 }; 1611 1612 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1613 mux { 1614 groups = "i2c_ao_sck_10"; 1615 function = "i2c_ao"; 1616 bias-disable; 1617 }; 1618 }; 1619 1620 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1621 mux { 1622 groups = "i2c_ao_sda_5"; 1623 function = "i2c_ao"; 1624 bias-disable; 1625 }; 1626 }; 1627 1628 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1629 mux { 1630 groups = "i2c_ao_sda_9"; 1631 function = "i2c_ao"; 1632 bias-disable; 1633 }; 1634 }; 1635 1636 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1637 mux { 1638 groups = "i2c_ao_sda_11"; 1639 function = "i2c_ao"; 1640 bias-disable; 1641 }; 1642 }; 1643 1644 remote_input_ao_pins: remote_input_ao { 1645 mux { 1646 groups = "remote_input_ao"; 1647 function = "remote_input_ao"; 1648 bias-disable; 1649 }; 1650 }; 1651 1652 uart_ao_a_pins: uart_ao_a { 1653 mux { 1654 groups = "uart_ao_tx_a", 1655 "uart_ao_rx_a"; 1656 function = "uart_ao_a"; 1657 bias-disable; 1658 }; 1659 }; 1660 1661 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1662 mux { 1663 groups = "uart_ao_cts_a", 1664 "uart_ao_rts_a"; 1665 function = "uart_ao_a"; 1666 bias-disable; 1667 }; 1668 }; 1669 1670 uart_ao_b_pins: uart_ao_b { 1671 mux { 1672 groups = "uart_ao_tx_b", 1673 "uart_ao_rx_b"; 1674 function = "uart_ao_b"; 1675 bias-disable; 1676 }; 1677 }; 1678 1679 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1680 mux { 1681 groups = "uart_ao_cts_b", 1682 "uart_ao_rts_b"; 1683 function = "uart_ao_b"; 1684 bias-disable; 1685 }; 1686 }; 1687 }; 1688 1689 sec_AO: ao-secure@140 { 1690 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1691 reg = <0x0 0x140 0x0 0x140>; 1692 amlogic,has-chip-id; 1693 }; 1694 1695 pwm_AO_cd: pwm@2000 { 1696 compatible = "amlogic,meson-axg-ao-pwm"; 1697 reg = <0x0 0x02000 0x0 0x20>; 1698 #pwm-cells = <3>; 1699 status = "disabled"; 1700 }; 1701 1702 uart_AO: serial@3000 { 1703 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1704 reg = <0x0 0x3000 0x0 0x18>; 1705 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1706 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1707 clock-names = "xtal", "pclk", "baud"; 1708 status = "disabled"; 1709 }; 1710 1711 uart_AO_B: serial@4000 { 1712 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1713 reg = <0x0 0x4000 0x0 0x18>; 1714 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1715 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1716 clock-names = "xtal", "pclk", "baud"; 1717 status = "disabled"; 1718 }; 1719 1720 i2c_AO: i2c@5000 { 1721 compatible = "amlogic,meson-axg-i2c"; 1722 reg = <0x0 0x05000 0x0 0x20>; 1723 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1724 clocks = <&clkc CLKID_AO_I2C>; 1725 #address-cells = <1>; 1726 #size-cells = <0>; 1727 status = "disabled"; 1728 }; 1729 1730 pwm_AO_ab: pwm@7000 { 1731 compatible = "amlogic,meson-axg-ao-pwm"; 1732 reg = <0x0 0x07000 0x0 0x20>; 1733 #pwm-cells = <3>; 1734 status = "disabled"; 1735 }; 1736 1737 ir: ir@8000 { 1738 compatible = "amlogic,meson-gxbb-ir"; 1739 reg = <0x0 0x8000 0x0 0x20>; 1740 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1741 status = "disabled"; 1742 }; 1743 1744 saradc: adc@9000 { 1745 compatible = "amlogic,meson-axg-saradc", 1746 "amlogic,meson-saradc"; 1747 reg = <0x0 0x9000 0x0 0x38>; 1748 #io-channel-cells = <1>; 1749 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1750 clocks = <&xtal>, 1751 <&clkc_AO CLKID_AO_SAR_ADC>, 1752 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1753 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1754 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1755 status = "disabled"; 1756 }; 1757 }; 1758 1759 ge2d: ge2d@ff940000 { 1760 compatible = "amlogic,axg-ge2d"; 1761 reg = <0x0 0xff940000 0x0 0x10000>; 1762 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 1763 clocks = <&clkc CLKID_VAPB>; 1764 resets = <&reset RESET_GE2D>; 1765 }; 1766 1767 gic: interrupt-controller@ffc01000 { 1768 compatible = "arm,gic-400"; 1769 reg = <0x0 0xffc01000 0 0x1000>, 1770 <0x0 0xffc02000 0 0x2000>, 1771 <0x0 0xffc04000 0 0x2000>, 1772 <0x0 0xffc06000 0 0x2000>; 1773 interrupt-controller; 1774 interrupts = <GIC_PPI 9 1775 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1776 #interrupt-cells = <3>; 1777 #address-cells = <0>; 1778 }; 1779 1780 cbus: bus@ffd00000 { 1781 compatible = "simple-bus"; 1782 reg = <0x0 0xffd00000 0x0 0x25000>; 1783 #address-cells = <2>; 1784 #size-cells = <2>; 1785 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 1786 1787 reset: reset-controller@1004 { 1788 compatible = "amlogic,meson-axg-reset"; 1789 reg = <0x0 0x01004 0x0 0x9c>; 1790 #reset-cells = <1>; 1791 }; 1792 1793 gpio_intc: interrupt-controller@f080 { 1794 compatible = "amlogic,meson-axg-gpio-intc", 1795 "amlogic,meson-gpio-intc"; 1796 reg = <0x0 0xf080 0x0 0x10>; 1797 interrupt-controller; 1798 #interrupt-cells = <2>; 1799 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 1800 }; 1801 1802 watchdog@f0d0 { 1803 compatible = "amlogic,meson-gxbb-wdt"; 1804 reg = <0x0 0xf0d0 0x0 0x10>; 1805 clocks = <&xtal>; 1806 }; 1807 1808 pwm_ab: pwm@1b000 { 1809 compatible = "amlogic,meson-axg-ee-pwm"; 1810 reg = <0x0 0x1b000 0x0 0x20>; 1811 #pwm-cells = <3>; 1812 status = "disabled"; 1813 }; 1814 1815 pwm_cd: pwm@1a000 { 1816 compatible = "amlogic,meson-axg-ee-pwm"; 1817 reg = <0x0 0x1a000 0x0 0x20>; 1818 #pwm-cells = <3>; 1819 status = "disabled"; 1820 }; 1821 1822 spicc0: spi@13000 { 1823 compatible = "amlogic,meson-axg-spicc"; 1824 reg = <0x0 0x13000 0x0 0x3c>; 1825 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1826 clocks = <&clkc CLKID_SPICC0>; 1827 clock-names = "core"; 1828 #address-cells = <1>; 1829 #size-cells = <0>; 1830 status = "disabled"; 1831 }; 1832 1833 spicc1: spi@15000 { 1834 compatible = "amlogic,meson-axg-spicc"; 1835 reg = <0x0 0x15000 0x0 0x3c>; 1836 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1837 clocks = <&clkc CLKID_SPICC1>; 1838 clock-names = "core"; 1839 #address-cells = <1>; 1840 #size-cells = <0>; 1841 status = "disabled"; 1842 }; 1843 1844 clk_msr: clock-measure@18000 { 1845 compatible = "amlogic,meson-axg-clk-measure"; 1846 reg = <0x0 0x18000 0x0 0x10>; 1847 }; 1848 1849 i2c3: i2c@1c000 { 1850 compatible = "amlogic,meson-axg-i2c"; 1851 reg = <0x0 0x1c000 0x0 0x20>; 1852 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1853 clocks = <&clkc CLKID_I2C>; 1854 #address-cells = <1>; 1855 #size-cells = <0>; 1856 status = "disabled"; 1857 }; 1858 1859 i2c2: i2c@1d000 { 1860 compatible = "amlogic,meson-axg-i2c"; 1861 reg = <0x0 0x1d000 0x0 0x20>; 1862 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1863 clocks = <&clkc CLKID_I2C>; 1864 #address-cells = <1>; 1865 #size-cells = <0>; 1866 status = "disabled"; 1867 }; 1868 1869 i2c1: i2c@1e000 { 1870 compatible = "amlogic,meson-axg-i2c"; 1871 reg = <0x0 0x1e000 0x0 0x20>; 1872 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1873 clocks = <&clkc CLKID_I2C>; 1874 #address-cells = <1>; 1875 #size-cells = <0>; 1876 status = "disabled"; 1877 }; 1878 1879 i2c0: i2c@1f000 { 1880 compatible = "amlogic,meson-axg-i2c"; 1881 reg = <0x0 0x1f000 0x0 0x20>; 1882 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1883 clocks = <&clkc CLKID_I2C>; 1884 #address-cells = <1>; 1885 #size-cells = <0>; 1886 status = "disabled"; 1887 }; 1888 1889 uart_B: serial@23000 { 1890 compatible = "amlogic,meson-gx-uart"; 1891 reg = <0x0 0x23000 0x0 0x18>; 1892 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1893 status = "disabled"; 1894 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1895 clock-names = "xtal", "pclk", "baud"; 1896 }; 1897 1898 uart_A: serial@24000 { 1899 compatible = "amlogic,meson-gx-uart"; 1900 reg = <0x0 0x24000 0x0 0x18>; 1901 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1902 status = "disabled"; 1903 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1904 clock-names = "xtal", "pclk", "baud"; 1905 fifo-size = <128>; 1906 }; 1907 }; 1908 1909 apb: bus@ffe00000 { 1910 compatible = "simple-bus"; 1911 reg = <0x0 0xffe00000 0x0 0x200000>; 1912 #address-cells = <2>; 1913 #size-cells = <2>; 1914 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 1915 1916 sd_emmc_b: mmc@5000 { 1917 compatible = "amlogic,meson-axg-mmc"; 1918 reg = <0x0 0x5000 0x0 0x800>; 1919 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 1920 status = "disabled"; 1921 clocks = <&clkc CLKID_SD_EMMC_B>, 1922 <&clkc CLKID_SD_EMMC_B_CLK0>, 1923 <&clkc CLKID_FCLK_DIV2>; 1924 clock-names = "core", "clkin0", "clkin1"; 1925 resets = <&reset RESET_SD_EMMC_B>; 1926 }; 1927 1928 sd_emmc_c: mmc@7000 { 1929 compatible = "amlogic,meson-axg-mmc"; 1930 reg = <0x0 0x7000 0x0 0x800>; 1931 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 1932 status = "disabled"; 1933 clocks = <&clkc CLKID_SD_EMMC_C>, 1934 <&clkc CLKID_SD_EMMC_C_CLK0>, 1935 <&clkc CLKID_FCLK_DIV2>; 1936 clock-names = "core", "clkin0", "clkin1"; 1937 resets = <&reset RESET_SD_EMMC_C>; 1938 }; 1939 1940 nfc: nand-controller@7800 { 1941 compatible = "amlogic,meson-axg-nfc"; 1942 reg = <0x0 0x7800 0x0 0x100>, 1943 <0x0 0x7000 0x0 0x800>; 1944 reg-names = "nfc", "emmc"; 1945 pinctrl-0 = <&nand_all_pins>; 1946 pinctrl-names = "default"; 1947 #address-cells = <1>; 1948 #size-cells = <0>; 1949 interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; 1950 clocks = <&clkc CLKID_SD_EMMC_C>, 1951 <&clkc CLKID_FCLK_DIV2>; 1952 clock-names = "core", "device"; 1953 }; 1954 1955 usb2_phy1: phy@9020 { 1956 compatible = "amlogic,meson-gxl-usb2-phy"; 1957 #phy-cells = <0>; 1958 reg = <0x0 0x9020 0x0 0x20>; 1959 clocks = <&clkc CLKID_USB>; 1960 clock-names = "phy"; 1961 resets = <&reset RESET_USB_OTG>; 1962 reset-names = "phy"; 1963 }; 1964 }; 1965 1966 sram: sram@fffc0000 { 1967 compatible = "mmio-sram"; 1968 reg = <0x0 0xfffc0000 0x0 0x20000>; 1969 #address-cells = <1>; 1970 #size-cells = <1>; 1971 ranges = <0 0x0 0xfffc0000 0x20000>; 1972 1973 cpu_scp_lpri: scp-sram@13000 { 1974 compatible = "amlogic,meson-axg-scp-shmem"; 1975 reg = <0x13000 0x400>; 1976 }; 1977 1978 cpu_scp_hpri: scp-sram@13400 { 1979 compatible = "amlogic,meson-axg-scp-shmem"; 1980 reg = <0x13400 0x400>; 1981 }; 1982 }; 1983 }; 1984 1985 timer { 1986 compatible = "arm,armv8-timer"; 1987 interrupts = <GIC_PPI 13 1988 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1989 <GIC_PPI 14 1990 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1991 <GIC_PPI 11 1992 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1993 <GIC_PPI 10 1994 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 1995 }; 1996 1997 xtal: xtal-clk { 1998 compatible = "fixed-clock"; 1999 clock-frequency = <24000000>; 2000 clock-output-names = "xtal"; 2001 #clock-cells = <0>; 2002 }; 2003}; 2004