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/linux/include/drm/display/
H A Ddrm_dp_helper.h47 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
49 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
134 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
135 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
140 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_link_rate()
142 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); in drm_dp_max_link_rate()
146 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_lane_count()
148 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in drm_dp_max_lane_count()
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/linux/drivers/gpu/drm/display/
H A Ddrm_dp_helper.c69 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
281 * - DPCD rev 1.3 vs. later
283 * Get the correct delay in us, reading DPCD if necessary.
285 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in __read_delay()
301 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in __read_delay()
327 rd_interval = dpcd[offset]; in __read_delay()
340 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_clock_recovery_delay()
343 return __read_delay(aux, dpcd, dp_phy, uhbr, true); in drm_dp_read_clock_recovery_delay()
347 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_channel_eq_delay()
350 return __read_delay(aux, dpcd, dp_phy, uhbr, false); in drm_dp_read_channel_eq_delay()
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/linux/drivers/gpu/drm/amd/display/include/
H A Dddc_service_types.h122 uint8_t av_granularity;/* DPCD 00023h */
123 uint8_t aud_dec_lat1;/* DPCD 00024h */
124 uint8_t aud_dec_lat2;/* DPCD 00025h */
125 uint8_t aud_pp_lat1;/* DPCD 00026h */
126 uint8_t aud_pp_lat2;/* DPCD 00027h */
127 uint8_t vid_inter_lat;/* DPCD 00028h */
128 uint8_t vid_prog_lat;/* DPCD 00029h */
129 uint8_t aud_del_ins1;/* DPCD 0002Bh */
130 uint8_t aud_del_ins2;/* DPCD 0002Ch */
131 uint8_t aud_del_ins3;/* DPCD 0002Dh */
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_dp.c42 return drm_dp_read_sink_count_cap(connector, outp->dp.dpcd, &outp->dp.desc); in nouveau_dp_has_sink_count()
69 u8 *dpcd = outp->dp.dpcd; in nouveau_dp_probe_dpcd() local
78 !drm_dp_read_dpcd_caps(aux, dpcd) && in nouveau_dp_probe_dpcd()
79 !drm_dp_read_lttpr_common_caps(aux, dpcd, outp->dp.lttpr.caps)) { in nouveau_dp_probe_dpcd()
99 ret = drm_dp_read_dpcd_caps(aux, dpcd); in nouveau_dp_probe_dpcd()
103 outp->dp.link_nr = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in nouveau_dp_probe_dpcd()
114 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP && dpcd[DP_DPCD_REV] >= 0x13) { in nouveau_dp_probe_dpcd()
134 outp->dp.rate[j].dpcd = i; in nouveau_dp_probe_dpcd()
143 u32 max_rate = dpcd[DP_MAX_LINK_RATE] * 27000; in nouveau_dp_probe_dpcd()
156 outp->dp.rate[outp->dp.rate_nr].dpcd = -1; in nouveau_dp_probe_dpcd()
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/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix-anx6345.c63 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
99 u8 dp_bw, dpcd[2]; in anx6345_dp_link_training() local
132 /* Get DPCD info */ in anx6345_dp_link_training()
134 &anx6345->dpcd, DP_RECEIVER_CAP_SIZE); in anx6345_dp_link_training()
136 DRM_ERROR("Failed to read DPCD: %d\n", err); in anx6345_dp_link_training()
147 * Power up the sink (DP_SET_POWER register is only available on DPCD in anx6345_dp_link_training()
150 if (anx6345->dpcd[DP_DPCD_REV] >= 0x11) { in anx6345_dp_link_training()
151 err = drm_dp_dpcd_readb(&anx6345->aux, DP_SET_POWER, &dpcd[0]); in anx6345_dp_link_training()
158 dpcd[0] &= ~DP_SET_POWER_MASK; in anx6345_dp_link_training()
159 dpcd[0] |= DP_SET_POWER_D0; in anx6345_dp_link_training()
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H A Danalogix-anx78xx.c83 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
606 u8 dp_bw, dpcd[2]; in anx78xx_dp_link_training() local
645 /* Get DPCD info */ in anx78xx_dp_link_training()
647 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE); in anx78xx_dp_link_training()
649 DRM_ERROR("Failed to read DPCD: %d\n", err); in anx78xx_dp_link_training()
660 * Power up the sink (DP_SET_POWER register is only available on DPCD in anx78xx_dp_link_training()
663 if (anx78xx->dpcd[DP_DPCD_REV] >= 0x11) { in anx78xx_dp_link_training()
664 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SET_POWER, &dpcd[0]); in anx78xx_dp_link_training()
671 dpcd[0] &= ~DP_SET_POWER_MASK; in anx78xx_dp_link_training()
672 dpcd[0] |= DP_SET_POWER_D0; in anx78xx_dp_link_training()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Datombios_dp.c253 const u8 dpcd[DP_DPCD_SIZE], in amdgpu_atombios_dp_get_dp_link_config()
260 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in amdgpu_atombios_dp_get_dp_link_config()
261 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in amdgpu_atombios_dp_get_dp_link_config()
322 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in amdgpu_atombios_dp_probe_oui()
339 if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) { in amdgpu_atombios_dp_ds_ports()
359 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in amdgpu_atombios_dp_get_dpcd()
361 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), in amdgpu_atombios_dp_get_dpcd()
362 dig_connector->dpcd); in amdgpu_atombios_dp_get_dpcd()
369 dig_connector->dpcd[0] = 0; in amdgpu_atombios_dp_get_dpcd()
421 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd, in amdgpu_atombios_dp_set_link_config()
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/linux/drivers/gpu/drm/msm/dp/
H A Ddp_panel.c35 if (dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) { in dp_panel_read_psr_cap()
53 u8 *dpcd, major, minor; in dp_panel_read_dpcd() local
56 dpcd = dp_panel->dpcd; in dp_panel_read_dpcd()
57 rc = drm_dp_read_dpcd_caps(panel->aux, dpcd); in dp_panel_read_dpcd()
61 dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd); in dp_panel_read_dpcd()
63 link_info->revision = dpcd[DP_DPCD_REV]; in dp_panel_read_dpcd()
67 link_info->rate = drm_dp_max_link_rate(dpcd); in dp_panel_read_dpcd()
68 link_info->num_lanes = drm_dp_max_lane_count(dpcd); in dp_panel_read_dpcd()
82 if (drm_dp_enhanced_frame_cap(dpcd)) in dp_panel_read_dpcd()
130 DRM_ERROR("read dpcd failed %d\n", rc); in dp_panel_read_sink_caps()
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H A Ddp_panel.h37 /* dpcd raw data */
38 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
/linux/drivers/gpu/drm/radeon/
H A Datombios_dp.c302 const u8 dpcd[DP_DPCD_SIZE], in radeon_dp_get_dp_link_config()
308 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in radeon_dp_get_dp_link_config()
309 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in radeon_dp_get_dp_link_config()
370 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in radeon_dp_probe_oui()
391 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in radeon_dp_getdpcd()
393 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), in radeon_dp_getdpcd()
394 dig_connector->dpcd); in radeon_dp_getdpcd()
401 dig_connector->dpcd[0] = 0; in radeon_dp_getdpcd()
458 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, in radeon_dp_set_link_config()
485 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, in radeon_dp_mode_valid_helper()
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/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_dpia.c229 /* Write training pattern to DPCD. */
274 * - Driver issues both DPCD and SET_CONFIG transactions.
339 /* Instruct DPOA to transmit TPS1 then update DPCD. */ in dpia_training_cr_non_transparent()
361 /* Update DPOA drive settings then DPCD. DPOA does only adjusts in dpia_training_cr_non_transparent()
386 /* Read status and adjustment requests from DPCD. */ in dpia_training_cr_non_transparent()
443 * - Driver only issues DPCD transactions and leaves USB4 tunneling (SET_CONFIG) messages to DPIA.
444 * - Driver writes TPS1 to DPCD to kick off training.
446 * - DPIA communicates result to driver by updating CR status when driver reads DPCD.
476 /* Write TPS1 (not VS or PE) to DPCD to start CR phase. in dpia_training_cr_transparent()
490 /* Read status and adjustment requests from DPCD. */ in dpia_training_cr_transparent()
[all …]
H A Dlink_dpcd.c28 * This file implements basic dpcd read/write functionality. It also does basic
29 * dpcd range check to ensure that every dpcd request is compliant with specs
75 * Partition the entire DPCD address space
76 * XXX: This partitioning must cover the entire DPCD address space,
100 /* all remaining DPCD addresses */
129 * Ranges of DPCD addresses that must be read in a single transaction
H A Dlink_dp_training.h62 /* Write DPCD drive settings. */
68 /* Write DPCD link configuration data. */
79 /* Read training status and adjustment requests from DPCD. */
133 /* Check DPCD training status registers to detect link loss. */
/linux/drivers/gpu/drm/i915/gvt/
H A Ddisplay.h62 /* DPCD start */
65 /* DPCD */
78 /* DPCD addresses */
106 /* DPCD end */
165 /* per display DPCD information */
166 struct intel_vgpu_dpcd_data *dpcd; member
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Ddp.h11 /* DPCD Receiver Capabilities */
26 /* DPCD Link Configuration */
52 /* DPCD Link/Sink Status */
87 /* DPCD Sink Control */
H A Ddp.c242 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x14 && in nvkm_dp_train_eq()
243 lt->outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_TPS4_SUPPORTED) in nvkm_dp_train_eq()
246 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x12 && in nvkm_dp_train_eq()
247 lt->outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED) in nvkm_dp_train_eq()
252 usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000; in nvkm_dp_train_eq()
284 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] < 0x14 && !lt->repeater) in nvkm_dp_train_cr()
285 usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000; in nvkm_dp_train_cr()
318 .pc2 = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED, in nvkm_dp_train_link()
327 sink[0] = (outp->dp.rate[rate].dpcd < 0) ? ior->dp.bw : 0; in nvkm_dp_train_link()
338 if (outp->dp.rate[rate].dpcd >= 0) { in nvkm_dp_train_link()
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/linux/drivers/gpu/drm/tegra/
H A Ddp.c172 u8 dpcd[DP_RECEIVER_CAP_SIZE], value; in drm_dp_link_probe() local
178 err = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, sizeof(dpcd)); in drm_dp_link_probe()
182 link->revision = dpcd[DP_DPCD_REV]; in drm_dp_link_probe()
183 link->max_rate = drm_dp_max_link_rate(dpcd); in drm_dp_link_probe()
184 link->max_lanes = drm_dp_max_lane_count(dpcd); in drm_dp_link_probe()
186 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd); in drm_dp_link_probe()
187 link->caps.tps3_supported = drm_dp_tps3_supported(dpcd); in drm_dp_link_probe()
188 link->caps.fast_training = drm_dp_fast_training_cap(dpcd); in drm_dp_link_probe()
189 link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd); in drm_dp_link_probe()
191 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { in drm_dp_link_probe()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_lspcon.c87 if (drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, drm_dp_is_branch(intel_dp->dpcd))) { in lspcon_detect_vendor()
237 drm_dbg_kms(display->drm, "Native AUX CH up, DPCD version: %d.%d\n", in lspcon_wake_native_aux_ch()
428 /* DPCD write for AVI IF can fail on a slow FW day, so retry */ in _lspcon_write_avi_infoframe_mca()
437 drm_err(aux->drm_dev, "DPCD write failed at:0x%x\n", reg); in _lspcon_write_avi_infoframe_mca()
448 drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg); in _lspcon_write_avi_infoframe_mca()
458 drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg); in _lspcon_write_avi_infoframe_mca()
465 drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg); in _lspcon_write_avi_infoframe_mca()
602 drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg); in _lspcon_read_avi_infoframe_enabled_mca()
617 drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg); in _lspcon_read_avi_infoframe_enabled_parade()
674 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) { in lspcon_init()
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H A Dintel_dp.c174 return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); in max_dprx_rate()
182 return drm_dp_max_lane_count(intel_dp->dpcd); in max_dprx_lane_count()
191 /* update sink rates from dpcd */
228 if (drm_dp_128b132b_supported(intel_dp->dpcd)) { in intel_dp_set_dpcd_sink_rates()
274 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n", in intel_dp_set_sink_rates()
302 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n", in intel_dp_set_max_sink_lane_count()
1037 if (!drm_dp_is_branch(intel_dp->dpcd)) in dfp_can_convert_from_rgb()
1054 if (!drm_dp_is_branch(intel_dp->dpcd)) in dfp_can_convert_from_ycbcr444()
1092 (!drm_dp_is_branch(intel_dp->dpcd) || in intel_dp_output_format()
1824 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and in intel_dp_dsc_compute_params()
[all …]
H A Dintel_dp_link_training.c73 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in intel_dp_read_lttpr_phy_caps()
78 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { in intel_dp_read_lttpr_phy_caps()
89 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_read_lttpr_common_caps()
93 ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd, in intel_dp_read_lttpr_common_caps()
143 static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_init_lttpr_phys()
147 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) in intel_dp_init_lttpr_phys()
204 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_init_lttpr()
209 lttpr_count = intel_dp_init_lttpr_phys(intel_dp, dpcd); in intel_dp_init_lttpr()
212 intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i)); in intel_dp_init_lttpr()
217 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_read_dprx_caps()
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/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c263 uint8_t dpcd[4]; member
326 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { in cdv_intel_dp_max_lane_count()
327 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; in cdv_intel_dp_max_lane_count()
342 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; in cdv_intel_dp_max_link_bw()
1073 * Check for DPCD version > 1.1 and enhanced framing support in cdv_intel_dp_mode_set()
1075 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && in cdv_intel_dp_mode_set()
1076 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { in cdv_intel_dp_mode_set()
1110 /* Should have a valid DPCD by this point */ in cdv_intel_dp_sink_dpms()
1111 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in cdv_intel_dp_sink_dpms()
1670 if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd, in cdv_dp_detect()
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/linux/drivers/gpu/drm/bridge/
H A Dite-it6505.c428 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
609 dev_err(dev, "DPCD read failed [0x%lx] ret: %d", offset, ret); in it6505_dpcd_read()
623 dev_err(dev, "DPCD write failed [0x%lx] ret: %d", offset, ret); in it6505_dpcd_write()
629 static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num) in it6505_get_dpcd() argument
634 ret = drm_dp_dpcd_read(&it6505->aux, offset, dpcd, num); in it6505_get_dpcd()
639 DRM_DEV_DEBUG_DRIVER(dev, "ret = %d DPCD[0x%x] = 0x%*ph", ret, offset, in it6505_get_dpcd()
640 num, dpcd); in it6505_get_dpcd()
757 /* DP_SET_POWER register is only available on DPCD v1.1 and later */ in it6505_drm_dp_link_set_power()
1451 return it6505->dpcd[DP_TRAINING_AUX_RD_INTERVAL] >= 0x01; in it6505_use_step_train_check()
1462 if (it6505->dpcd[0] == 0) { in it6505_parse_link_capabilities()
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dp_types.h333 /* The DPCD addresses are from 0x103 to 0x106*/
603 /*DPCD register of DP receiver capability field bits-*/
736 /* FEC capability DPCD register field bits-*/
751 /* DSC capability DPCD register field bits-*/
863 /* These parameters are from PSR capabilities reported by Sink DPCD */
894 /* Length of router topology ID read from DPCD in bytes. */
897 /* DPCD[0xE000D] DP_TUNNELING_CAPABILITIES SUPPORT register. */
908 /* DPCD[0xE000E] DP_IN_ADAPTER_INFO register. */
1340 /* TODO - This is a temporary location for any new DPCD definitions.
1361 /** USB4 DPCD BW Allocation Registers Chapter 10.7 **/
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_helpers.c68 /* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */ in apply_edid_quirks()
74 DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id); in apply_edid_quirks()
295 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or in dm_helpers_dp_mst_write_payload_allocation_table()
529 DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0], in dm_helpers_dp_mst_start_top_mgr()
530 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK); in dm_helpers_dp_mst_start_top_mgr()
767 "MST_DSC Configure DSC to non-virtual dpcd synaptics\n"); in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
783 /* Synaptics hub not support virtual dpcd, in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
831 "MST_DSC Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", in dm_helpers_dp_write_dsc_enable()
840 "virtual dpcd", in dm_helpers_dp_write_dsc_enable()
848 "virtual dpcd", in dm_helpers_dp_write_dsc_enable()
[all …]
/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-mhdp8546-core.c338 dev_err(mhdp->dev, "dpcd write failed: %d\n", ret); in cdns_mhdp_dpcd_write()
499 u8 hdr[5]; /* For DPCD read response header */ in cdns_mhdp_adjust_lt()
521 /* Yes, read the DPCD read command response */ in cdns_mhdp_adjust_lt()
561 /* DP_SET_POWER register is only available on DPCD v1.1 and later */ in cdns_mhdp_link_power_up()
600 /* DP_SET_POWER register is only available on DPCD v1.1 and later */ in cdns_mhdp_link_power_down()
856 "Failed to write DPCD addr %u\n", in cdns_mhdp_transfer()
866 "Failed to read DPCD addr %u\n", in cdns_mhdp_transfer()
1366 "wrong training interval returned by DPCD: %d\n", interval); in cdns_mhdp_get_training_interval_us()
1401 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in cdns_mhdp_fill_sink_caps()
1409 mhdp->sink.ssc = !!(dpcd[DP_MAX_DOWNSPREAD] & in cdns_mhdp_fill_sink_caps()
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