Lines Matching full:dpcd
174 return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); in max_dprx_rate()
182 return drm_dp_max_lane_count(intel_dp->dpcd); in max_dprx_lane_count()
191 /* update sink rates from dpcd */
228 if (drm_dp_128b132b_supported(intel_dp->dpcd)) { in intel_dp_set_dpcd_sink_rates()
274 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n", in intel_dp_set_sink_rates()
302 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n", in intel_dp_set_max_sink_lane_count()
1037 if (!drm_dp_is_branch(intel_dp->dpcd)) in dfp_can_convert_from_rgb()
1054 if (!drm_dp_is_branch(intel_dp->dpcd)) in dfp_can_convert_from_ycbcr444()
1092 (!drm_dp_is_branch(intel_dp->dpcd) || in intel_dp_output_format()
1824 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and in intel_dp_dsc_compute_params()
1945 * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate in intel_dp_dsc_max_sink_compressed_bppx16()
3072 drm_dp_enhanced_frame_cap(intel_dp->dpcd); in intel_dp_compute_config()
3182 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus in downstream_hpd_needs_d0()
3189 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && in downstream_hpd_needs_d0()
3190 drm_dp_is_branch(intel_dp->dpcd) && in downstream_hpd_needs_d0()
3308 * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3342 * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3412 /* Should have a valid DPCD by this point */ in intel_dp_set_power()
3413 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_set_power()
3469 * Don't clobber DPCD if it's been already read out during output in intel_dp_sync_state()
3472 if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) { in intel_dp_sync_state()
3541 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n", in intel_dp_get_pcon_dsc_cap()
3544 drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n", in intel_dp_get_pcon_dsc_cap()
3683 if (drm_dp_is_branch(intel_dp->dpcd) && in intel_dp_is_hdmi_2_1_sink()
3846 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) in intel_dp_configure_protocol_converter()
3849 if (!drm_dp_is_branch(intel_dp->dpcd)) in intel_dp_configure_protocol_converter()
3919 "Failed to read DPCD register 0x%x\n", in intel_dp_read_dsc_dpcd()
3924 drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n", in intel_dp_read_dsc_dpcd()
3950 drm_err(&i915->drm, "Failed to read FEC DPCD register\n"); in intel_dp_get_dsc_sink_cap()
4035 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) { in intel_edp_mso_init()
4042 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso, in intel_edp_mso_init()
4061 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); in intel_edp_init_dpcd()
4063 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) in intel_edp_init_dpcd()
4067 drm_dp_is_branch(intel_dp->dpcd)); in intel_edp_init_dpcd()
4085 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n", in intel_edp_init_dpcd()
4136 /* Read the eDP DSC DPCD registers */ in intel_edp_init_dpcd()
4157 intel_dp->dpcd, in intel_dp_has_sink_count()
4182 drm_dp_is_branch(intel_dp->dpcd)); in intel_dp_get_dpcd()
4215 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd, in intel_dp_get_dpcd()
4242 !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B)) in intel_dp_mst_mode_choose()
4256 sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); in intel_dp_mst_detect()
4959 * FIXME: Ideally pattern should come from DPCD 0x250. As in intel_dp_phy_pattern_update()
4977 * FIXME: Ideally pattern should come from DPCD 0x24A. As in intel_dp_phy_pattern_update()
5029 intel_dp->dpcd[DP_DPCD_REV]); in intel_dp_process_phy_request()
5565 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_check_device_service_irq()
5590 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_check_link_service_irq()
5615 * 1. Read DPCD
5640 * Now read the DPCD to see if it's actually running in intel_dp_short_pulse()
5642 * the value that was stored earlier or dpcd read failed in intel_dp_short_pulse()
5690 u8 *dpcd = intel_dp->dpcd; in intel_dp_detect_dpcd() local
5704 if (!drm_dp_is_branch(dpcd)) in intel_dp_detect_dpcd()
5722 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { in intel_dp_detect_dpcd()
5728 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & in intel_dp_detect_dpcd()
5835 drm_dp_downstream_max_bpc(intel_dp->dpcd, in intel_dp_update_dfp()
5839 drm_dp_downstream_max_dotclock(intel_dp->dpcd, in intel_dp_update_dfp()
5843 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd, in intel_dp_update_dfp()
5847 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd, in intel_dp_update_dfp()
5852 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, in intel_dp_update_dfp()
5871 (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough)) in intel_dp_can_ycbcr420()
5892 drm_dp_downstream_420_passthrough(intel_dp->dpcd, in intel_dp_update_420()
5897 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, in intel_dp_update_420()
5900 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, in intel_dp_update_420()
5969 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ in intel_dp_detect_dsc_caps()
5977 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], in intel_dp_detect_dsc_caps()
5987 drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd); in intel_dp_detect_sdp_caps()
6114 intel_dp->dpcd, in intel_dp_detect()
6161 intel_dp->dpcd, in intel_dp_get_modes()
6471 u8 dpcd[DP_RECEIVER_CAP_SIZE]; in intel_dp_hpd_pulse() local
6503 intel_dp_read_dprx_caps(intel_dp, dpcd); in intel_dp_hpd_pulse()
6690 * The DPCD probe below will make sure VDD is on. in intel_edp_init_connector()
6696 /* Cache DPCD and EDID for edp. */ in intel_edp_init_connector()
6717 * If this fails, presume the DPCD answer came in intel_edp_init_connector()
6721 * DPCD read? Would need sort out the VDD handling... in intel_edp_init_connector()
6736 if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) && in intel_edp_init_connector()
6737 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) == in intel_edp_init_connector()