63 	u8 dpcd[DP_RECEIVER_CAP_SIZE];  member
99 	u8 dp_bw, dpcd[2];  in anx6345_dp_link_training()  local
132 	/* Get DPCD info */  in anx6345_dp_link_training()
134 			       &anx6345->dpcd, DP_RECEIVER_CAP_SIZE);  in anx6345_dp_link_training()
136 		DRM_ERROR("Failed to read DPCD: %d\n", err);  in anx6345_dp_link_training()
147 	 * Power up the sink (DP_SET_POWER register is only available on DPCD  in anx6345_dp_link_training()
150 	if (anx6345->dpcd[DP_DPCD_REV] >= 0x11) {  in anx6345_dp_link_training()
151 		err = drm_dp_dpcd_readb(&anx6345->aux, DP_SET_POWER, &dpcd[0]);  in anx6345_dp_link_training()
158 		dpcd[0] &= ~DP_SET_POWER_MASK;  in anx6345_dp_link_training()
159 		dpcd[0] |= DP_SET_POWER_D0;  in anx6345_dp_link_training()
161 		err = drm_dp_dpcd_writeb(&anx6345->aux, DP_SET_POWER, dpcd[0]);  in anx6345_dp_link_training()
182 	if (anx6345->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {  in anx6345_dp_link_training()
201 	if (drm_dp_enhanced_frame_cap(anx6345->dpcd))  in anx6345_dp_link_training()
212 	dpcd[0] = dp_bw;  in anx6345_dp_link_training()
214 			   SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]);  in anx6345_dp_link_training()
218 	dpcd[1] = drm_dp_max_lane_count(anx6345->dpcd);  in anx6345_dp_link_training()
221 			   SP_DP_LANE_COUNT_SET_REG, dpcd[1]);  in anx6345_dp_link_training()
225 	if (drm_dp_enhanced_frame_cap(anx6345->dpcd))  in anx6345_dp_link_training()
226 		dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;  in anx6345_dp_link_training()
228 	err = drm_dp_dpcd_write(&anx6345->aux, DP_LINK_BW_SET, dpcd,  in anx6345_dp_link_training()
229 				sizeof(dpcd));  in anx6345_dp_link_training()