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/linux/Documentation/devicetree/bindings/display/msm/
H A Ddp-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MSM Display Port Controller
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
13 Device tree bindings for DisplayPort host controller for MSM targets
19 - enum:
20 - qcom,sc7180-dp
21 - qcom,sc7280-dp
[all …]
H A Dqcom,x1e80100-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abel Vesa <abel.vesa@linaro.org>
13 X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DP interfaces, etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,x1e80100-mdss
24 - description: Display AHB
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H A Dqcom,sc7280-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7280-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-usb43dp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,sc7180-qmp-usb3-dp-phy
20 - qcom,sc7280-qmp-usb3-dp-phy
21 - qcom,sc8180x-qmp-usb3-dp-phy
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H A Dsamsung,dp-video-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,dp-video-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
17 - samsung,exynos5250-dp-video-phy
18 - samsung,exynos5420-dp-video-phy
20 "#phy-cells":
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/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,dp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Display Port Controller
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Jitao shi <jitao.shi@mediatek.com>
14 MediaTek DP and eDP are different hardwares and there are some features
17 In addition, We just need to enable the power domain of DP, so the clock
18 of DP is generated by itself and we are not using other PLL to generate
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/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip,analogix-dp.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,analogix-dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
16 - rockchip,rk3288-dp
17 - rockchip,rk3399-edp
23 clock-names:
26 - const: dp
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/linux/drivers/gpu/drm/rockchip/
H A Danalogix_dp-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip SoC DP (Display Port) interface driver.
6 * Author: Andy Yan <andy.yan@rock-chips.com>
7 * Yakir Yang <ykk@rock-chips.com>
8 * Jeff Chen <jeff.chen@rock-chips.com>
45 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
87 static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) in rockchip_dp_pre_init() argument
89 reset_control_assert(dp->rst); in rockchip_dp_pre_init()
91 reset_control_deassert(dp->rst); in rockchip_dp_pre_init()
98 struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data); in rockchip_dp_poweron() local
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/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sm8450-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller for SM8450
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
16 See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h
21 - qcom,sm8450-dispcc
26 - description: Board XO source
27 - description: Board Always On XO source
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H A Dqcom,sm8550-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller for SM8550
10 - Bjorn Andersson <andersson@kernel.org>
11 - Neil Armstrong <neil.armstrong@linaro.org>
18 - include/dt-bindings/clock/qcom,sm8550-dispcc.h
19 - include/dt-bindings/clock/qcom,sm8650-dispcc.h
20 - include/dt-bindings/clock/qcom,x1e80100-dispcc.h
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/linux/Documentation/devicetree/bindings/soc/samsung/
H A Dexynos-pmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
18 - google,gs101-pmu
19 - samsung,exynos3250-pmu
20 - samsung,exynos4210-pmu
21 - samsung,exynos4212-pmu
22 - samsung,exynos4412-pmu
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/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,exynos5-dp.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos5-dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
17 const: samsung,exynos5-dp
25 clock-names:
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/linux/drivers/thunderbolt/
H A Dlc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt link controller support
14 * tb_lc_read_uuid() - Read switch UUID from link controller common register
20 if (!sw->cap_lc) in tb_lc_read_uuid()
21 return -EINVAL; in tb_lc_read_uuid()
22 return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4); in tb_lc_read_uuid()
27 if (!sw->cap_lc) in read_lc_desc()
28 return -EINVAL; in read_lc_desc()
29 return tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1); in read_lc_desc()
34 struct tb_switch *sw = port->sw; in find_port_lc_cap()
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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra124-sor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 and DP outputs.
19 pattern: "^sor@[0-9a-f]+$"
23 - enum:
24 - nvidia,tegra124-sor
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/linux/Documentation/devicetree/bindings/display/
H A Ddp-aux-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dp-aux-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Douglas Anderson <dianders@chromium.org>
14 are hooked up to them. This is the DP AUX bus. Over the DP AUX bus
16 particular, DP sinks support DDC over DP AUX which allows tunneling
19 To model this relationship, DP sinks should be placed as children
20 of the DP controller under the "aux-bus" node.
23 possible it will be extended in the future to handle the DP case.
[all …]
/linux/arch/sparc/kernel/
H A Dprom_irqtrans.c1 // SPDX-License-Identifier: GPL-2.0
44 static unsigned int psycho_irq_build(struct device_node *dp, in psycho_irq_build() argument
74 static void __init psycho_irq_trans_init(struct device_node *dp) in psycho_irq_trans_init() argument
78 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller)); in psycho_irq_trans_init()
79 dp->irq_trans->irq_build = psycho_irq_build; in psycho_irq_trans_init()
81 regs = of_get_property(dp, "reg", NULL); in psycho_irq_trans_init()
82 dp->irq_trans->data = (void *) regs[2].phys_addr; in psycho_irq_trans_init()
112 * side of the non-APB bridge, then perform a read of Sabre's DMA
113 * write-sync register.
119 unsigned long controller_regs = irq_data->controller_regs; in sabre_wsync_handler()
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/linux/drivers/gpu/drm/msm/dp/
H A Ddp_drm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
17 * dp_bridge_detect - callback to determine if connector is connected
23 struct msm_dp *dp; in dp_bridge_detect() local
25 dp = to_dp_bridge(bridge)->dp_display; in dp_bridge_detect()
27 drm_dbg_dp(dp->drm_dev, "link_ready = %s\n", in dp_bridge_detect()
28 (dp->link_ready) ? "true" : "false"); in dp_bridge_detect()
30 return (dp->link_ready) ? connector_status_connected : in dp_bridge_detect()
39 struct msm_dp *dp; in dp_bridge_atomic_check() local
41 dp = to_dp_bridge(bridge)->dp_display; in dp_bridge_atomic_check()
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/linux/drivers/ata/
H A Dpata_atp867x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pata_atp867x.c - ARTOP 867X 64bit 4-channel UDMA133 ATA controller driver
5 * (C) 2009 Google Inc. John(Jung-Ik) Lee <jilee@google.com>
9 * 2003-2004 by Eric Uhrhane, Google, Inc.
69 #define ATP867X_IOBASE(ap) ((ap)->host->iomap[0])
109 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in atp867x_set_dmamode()
110 struct atp867x_priv *dp = ap->private_data; in atp867x_set_dmamode() local
111 u8 speed = adev->dma_mode; in atp867x_set_dmamode()
113 u8 mode = speed - XFER_UDMA_0 + 1; in atp867x_set_dmamode()
118 * rev-A: UDMA_1~4 (5, 6 no change) in atp867x_set_dmamode()
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/linux/arch/sparc/include/asm/
H A Dfloppy_64.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #include <linux/dma-mapping.h>
28 * 2) NCR 82077 controller manual
29 * 3) Intel 82077 controller manual
44 /* You'll only ever find one controller on an Ultra anyways. */
45 static struct sun_flpy_controller *sun_fdc = (struct sun_flpy_controller *)-1;
109 return sbus_readb(&sun_fdc->status_82077) & ~STATUS_DMA; in sun_82077_fd_inb()
111 return sbus_readb(&sun_fdc->data_82077); in sun_82077_fd_inb()
114 return sbus_readb(&sun_fdc->dir_82077); in sun_82077_fd_inb()
129 sbus_writeb(value, &sun_fdc->dor_82077); in sun_82077_fd_outb()
[all …]
H A Dfloppy_32.h1 /* SPDX-License-Identifier: GPL-2.0 */
29 * 2) NCR 82077 controller manual
30 * 3) Intel 82077 controller manual
52 /* You'll only ever find one controller on a SparcStation anyways. */
102 /* Routines unique to each controller type on a Sun. */
106 sun_fdc->dor_82077 = value; in sun_set_dor()
111 return sun_fdc->dir_82077; in sun_read_dir()
122 return sun_fdc->status_82072 & ~STATUS_DMA; in sun_82072_fd_inb()
124 return sun_fdc->data_82072; in sun_82072_fd_inb()
142 sun_fdc->data_82072 = value; in sun_82072_fd_outb()
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/linux/Documentation/devicetree/bindings/display/connector/
H A Ddp-connector.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/connector/dp-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tomi Valkeinen <tomi.valkeinen@ti.com>
14 const: dp-connector
20 - full-size
21 - mini
23 hpd-gpios:
27 dp-pwr-supply:
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/linux/include/drm/display/
H A Ddrm_dp_helper.h75 * struct drm_dp_vsc_sdp - drm DP VSC SDP
77 * This structure represents a DP VSC SDP of drm
78 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
79 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
81 * @sdp_type: secondary-data packet type
88 * @content_type: CTA-861-G defines content types and expected processing by a sink device
102 * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP
104 * This structure represents a DP AS SDP of drm
105 * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes] and
106 * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8]
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/linux/drivers/usb/isp1760/
H A Disp1760-if.c1 // SPDX-License-Identifier: GPL-2.0
5 * - OpenFirmware
6 * - PCI
7 * - PDEV (generic platform device centralized driver model)
24 #include "isp1760-core.h"
25 #include "isp1760-regs.h"
46 return -ENOMEM; in isp1761_pci_init()
49 if (!request_mem_region(mem_start, mem_length, "ISP-PCI")) { in isp1761_pci_init()
50 printk(KERN_ERR "host controller already in use\n"); in isp1761_pci_init()
51 return -EBUSY; in isp1761_pci_init()
[all …]
/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_dpsub.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
43 * struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem
54 * @bridge: The DP encoder bridge
55 * @disp: The display controller
57 * @dp: The DisplayPort controller
77 struct zynqmp_dp *dp; member
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dcdns,mhdp8546.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
22 - description:
26 - description:
28 - description:
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