Lines Matching +full:dp +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Display Port Controller
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Jitao shi <jitao.shi@mediatek.com>
14 MediaTek DP and eDP are different hardwares and there are some features
17 In addition, We just need to enable the power domain of DP, so the clock
18 of DP is generated by itself and we are not using other PLL to generate
24 - mediatek,mt8188-dp-tx
25 - mediatek,mt8188-edp-tx
26 - mediatek,mt8195-dp-tx
27 - mediatek,mt8195-edp-tx
32 nvmem-cells:
36 nvmem-cell-names:
39 power-domains:
50 description: Input endpoint of the controller, usually dp_intf
53 $ref: /schemas/graph.yaml#/$defs/port-base
55 description: Output endpoint of the controller
58 $ref: /schemas/media/video-interfaces.yaml#
61 data-lanes:
65 0 - For 1 lane enabled in IP.
66 0 1 - For 2 lanes enabled in IP.
67 0 1 2 3 - For 4 lanes enabled in IP.
71 - data-lanes
74 - port@0
75 - port@1
77 max-linkrate-mhz:
82 - compatible
83 - reg
84 - interrupts
85 - ports
86 - max-linkrate-mhz
91 - |
92 #include <dt-bindings/interrupt-controller/arm-gic.h>
93 #include <dt-bindings/power/mt8195-power.h>
95 compatible = "mediatek,mt8195-dp-tx";
97 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
99 max-linkrate-mhz = <8100>;
102 #address-cells = <1>;
103 #size-cells = <0>;
108 remote-endpoint = <&dp_intf0_out>;
114 data-lanes = <0 1 2 3>;