Lines Matching +full:dp +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abel Vesa <abel.vesa@linaro.org>
13 X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DP interfaces, etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,x1e80100-mdss
24 - description: Display AHB
25 - description: Display hf AXI
26 - description: Display core
34 interconnect-names:
38 "^display-controller@[0-9a-f]+$":
43 const: qcom,x1e80100-dpu
45 "^displayport-controller@[0-9a-f]+$":
50 const: qcom,x1e80100-dp
52 "^phy@[0-9a-f]+$":
57 const: qcom,x1e80100-dp-phy
60 - compatible
65 - |
66 #include <dt-bindings/clock/qcom,rpmh.h>
67 #include <dt-bindings/interrupt-controller/arm-gic.h>
68 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
69 #include <dt-bindings/phy/phy-qcom-qmp.h>
70 #include <dt-bindings/power/qcom,rpmhpd.h>
72 display-subsystem@ae00000 {
73 compatible = "qcom,x1e80100-mdss";
75 reg-names = "mdss";
80 interconnect-names = "mdp0-mem", "mdp1-mem", "cpu-cfg";
84 power-domains = <&dispcc_gdsc>;
89 clock-names = "bus", "nrt_bus", "core";
92 interrupt-controller;
93 #interrupt-cells = <1>;
97 #address-cells = <1>;
98 #size-cells = <1>;
101 display-controller@ae01000 {
102 compatible = "qcom,x1e80100-dpu";
105 reg-names = "mdp", "vbif";
112 clock-names = "nrt_bus",
118 assigned-clocks = <&dispcc_mdp_vsync_clk>;
119 assigned-clock-rates = <19200000>;
121 operating-points-v2 = <&mdp_opp_table>;
122 power-domains = <&rpmhpd RPMHPD_MMCX>;
124 interrupt-parent = <&mdss>;
128 #address-cells = <1>;
129 #size-cells = <0>;
134 remote-endpoint = <&dsi0_in>;
141 remote-endpoint = <&dsi1_in>;
146 mdp_opp_table: opp-table {
147 compatible = "operating-points-v2";
149 opp-200000000 {
150 opp-hz = /bits/ 64 <200000000>;
151 required-opps = <&rpmhpd_opp_low_svs>;
154 opp-325000000 {
155 opp-hz = /bits/ 64 <325000000>;
156 required-opps = <&rpmhpd_opp_svs>;
159 opp-375000000 {
160 opp-hz = /bits/ 64 <375000000>;
161 required-opps = <&rpmhpd_opp_svs_l1>;
164 opp-514000000 {
165 opp-hz = /bits/ 64 <514000000>;
166 required-opps = <&rpmhpd_opp_nom>;
171 displayport-controller@ae90000 {
172 compatible = "qcom,x1e80100-dp";
179 interrupt-parent = <&mdss>;
187 clock-names = "core_iface", "core_aux",
192 assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
194 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
197 operating-points-v2 = <&mdss_dp0_opp_table>;
199 power-domains = <&rpmhpd RPMHPD_MMCX>;
202 phy-names = "dp";
204 #sound-dai-cells = <0>;
207 #address-cells = <1>;
208 #size-cells = <0>;
214 remote-endpoint = <&mdss_intf0_out>;
226 mdss_dp0_opp_table: opp-table {
227 compatible = "operating-points-v2";
229 opp-160000000 {
230 opp-hz = /bits/ 64 <160000000>;
231 required-opps = <&rpmhpd_opp_low_svs>;
234 opp-270000000 {
235 opp-hz = /bits/ 64 <270000000>;
236 required-opps = <&rpmhpd_opp_svs>;
239 opp-540000000 {
240 opp-hz = /bits/ 64 <540000000>;
241 required-opps = <&rpmhpd_opp_svs_l1>;
244 opp-810000000 {
245 opp-hz = /bits/ 64 <810000000>;
246 required-opps = <&rpmhpd_opp_nom>;