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/linux/drivers/memory/samsung/
H A Dexynos5422-dmc.c105 * Covers frequency and voltage settings of the DMC operating mode.
113 * struct exynos5_dmc - main structure describing DMC device
114 * @dev: DMC device
239 static int exynos5_counters_set_event(struct exynos5_dmc *dmc) in exynos5_counters_set_event() argument
243 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_set_event()
244 if (!dmc->counter[i]) in exynos5_counters_set_event()
246 ret = devfreq_event_set_event(dmc->counter[i]); in exynos5_counters_set_event()
253 static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc) in exynos5_counters_enable_edev() argument
257 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_enable_edev()
258 if (!dmc->counter[i]) in exynos5_counters_enable_edev()
[all …]
H A DKconfig17 This adds driver for Samsung Exynos5422 SoC DMC (Dynamic Memory
19 Frequency Scaling in DMC and DRAM. It also supports changing timings
H A DMakefile2 obj-$(CONFIG_EXYNOS5422_DMC) += exynos5422-dmc.o
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dmc.c36 * DOC: DMC Firmware Support
38 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
75 return i915->display.dmc.dmc; in i915_to_dmc()
101 * New DMC additions should not use this. This is used solely to remain
102 * compatible with systems that have not yet updated DMC blobs to use
231 /* 0x09 for DMC */
234 /* Includes the DMC specific header in dwords */
249 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
291 /* DMC container header length in dwords */
307 /* DMC binary header length */
[all …]
H A Dintel_dmc_wl.c14 * DOC: DMC wakelock support
26 * The wakelock mechanism in DMC allows the display engine to exit DC
30 * wakelock implementation, the driver asserts a wakelock in DMC,
84 WARN_RATELIMIT(1, "DMC wakelock release timed out"); in intel_dmc_wl_work()
126 /* don't call __intel_dmc_wl_supported(), DMC is not loaded yet */ in intel_dmc_wl_init()
149 * Enable wakelock in DMC. We shouldn't try to take the in intel_dmc_wl_enable()
177 /* Disable wakelock in DMC */ in intel_dmc_wl_disable()
225 WARN_RATELIMIT(1, "DMC wakelock ack timed out"); in intel_dmc_wl_get()
H A Dintel_display_params.c31 "DMC firmware path to use instead of the default one. "
32 "Use /dev/null to disable DMC and runtime PM.");
127 "Enable DMC wakelock "
H A Dintel_display_power_map.c358 /* Handled by the DMC firmware */
372 /* Handled by the DMC firmware */
611 * ICL PW_0/PG_0 domains (HW/DMC control):
616 * ICL PW_1/PG_1 domains (HW/DMC control):
717 /* Handled by the DMC firmware */
1034 * RKL PW_1/PG_1 domains (under HW/DMC control):
1041 * RKL PW_0/PG_0 domains (under HW/DMC control):
1283 * XELPD PW_1/PG_1 domains (under HW/DMC control):
1288 * XELPD PW_0/PW_1 domains (under HW/DMC control):
/linux/Documentation/devicetree/bindings/edac/
H A Ddmc-520.yaml4 $id: http://devicetree.org/schemas/edac/dmc-520.yaml#
7 title: ARM DMC-520 EDAC
13 DMC-520 node is defined to describe DRAM error detection and correction.
20 - const: brcm,dmc-520
21 - const: arm,dmc-520
56 dmc0: dmc@200000 {
57 compatible = "brcm,dmc-520", "arm,dmc-520";
/linux/Documentation/admin-guide/perf/
H A Dthunderx2-pmu.rst6 PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and
9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
13 The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 8
16 overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.
21 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
22 L3C devices. Each PMU can be used to count up to 4 (DMC/L3C) or up to 8
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dsamsung,exynos5422-dmc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
16 The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
22 switch the DMC and memory frequency.
27 - const: samsung,exynos5422-dmc
62 - description: DMC internal performance event counters in DREX0
63 - description: DMC internal performance event counters in DREX1
112 compatible = "samsung,exynos5422-dmc";
H A Dsamsung,s5pv210-dmc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/samsung,s5pv210-dmc.yaml#
17 const: samsung,s5pv210-dmc
31 compatible = "samsung,s5pv210-dmc";
H A Drockchip,rk3399-dmc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
7 title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
15 - rockchip,rk3399-dmc
34 DMC regulator supply.
363 compatible = "rockchip,rk3399-dmc";
/linux/drivers/pmdomain/amlogic/
H A Dmeson-secure-pwrc.c119 /* DMC is for DDR PHY ana/dig and DMC, and should be always on */
120 SEC_PD(DMC, GENPD_FLAG_ALWAYS_ON),
149 /* DMC is for DDR PHY ana/dig and DMC, and should be always on */
168 /* DMC is for DDR PHY ana/dig and DMC, and should be always on */
243 /* DMC0 is for DDR PHY ana/dig and DMC, and should be always on */
245 /* DMC1 is for DDR PHY ana/dig and DMC, and should be always on */
/linux/Documentation/devicetree/bindings/interconnect/
H A Dsamsung,exynos-bus.yaml49 VDD_MIF |--- DMC (Dynamic Memory Controller)
93 VDD_INT |--- DMC (parent device, Dynamic Memory Controller)
110 VDD_MIF |--- DMC (Dynamic Memory Controller)
225 bus-dmc {
287 dmc: bus-dmc {
303 interconnects = <&dmc>;
314 interconnects = <&leftbus &dmc>;
/linux/include/soc/amlogic/
H A Dmeson_ddr_pmu.h35 u64 channel_cnt[MAX_CHANNEL_NUM]; /* To save a DMC bandwidth-monitor channel counter */
48 int dmc_nr; /* The number of dmc controller */
49 int chann_nr; /* The number of dmc bandwidth monitor channels */
/linux/drivers/net/ethernet/sun/
H A Dniu.h19 #define DMC 0x600000UL macro
1978 #define RXDMA_CFIG1(IDX) (DMC + 0x00000UL + (IDX) * 0x200UL)
1984 #define RXDMA_CFIG2(IDX) (DMC + 0x00008UL + (IDX) * 0x200UL)
1990 #define RBR_CFIG_A(IDX) (DMC + 0x00010UL + (IDX) * 0x200UL)
1996 #define RBR_CFIG_B(IDX) (DMC + 0x00018UL + (IDX) * 0x200UL)
2026 #define RBR_KICK(IDX) (DMC + 0x00020UL + (IDX) * 0x200UL)
2029 #define RBR_STAT(IDX) (DMC + 0x00028UL + (IDX) * 0x200UL)
2032 #define RBR_HDH(IDX) (DMC + 0x00030UL + (IDX) * 0x200UL)
2035 #define RBR_HDL(IDX) (DMC + 0x00038UL + (IDX) * 0x200UL)
2038 #define RCRCFIG_A(IDX) (DMC + 0x00040UL + (IDX) * 0x200UL)
[all …]
/linux/drivers/cpufreq/
H A Ds5pv210-cpufreq.c194 * ch: DMC port number 0 or 1
207 pr_err("Cannot find DMC port\n"); in s5pv210_set_refresh()
536 /* Find current refresh counter and frequency each DMC */ in s5pv210_cpu_init()
599 * and DMC controller registers directly and remove static mappings in s5pv210_cpufreq_probe()
632 for_each_compatible_node(np, NULL, "samsung,s5pv210-dmc") { in s5pv210_cpufreq_probe()
633 id = of_alias_get_id(np, "dmc"); in s5pv210_cpufreq_probe()
635 dev_err(dev, "failed to get alias of dmc node '%pOFn'\n", np); in s5pv210_cpufreq_probe()
643 dev_err(dev, "failed to map dmc%d registers\n", id); in s5pv210_cpufreq_probe()
652 dev_err(dev, "failed to find dmc%d node\n", id); in s5pv210_cpufreq_probe()
/linux/drivers/acpi/apei/
H A Dhest.c51 struct acpi_hest_ia_deferred_check *dmc; member
99 mces.dmc = mc; in hest_esrc_len()
128 if (mces.dmc && mces.dmc->flags & ACPI_HEST_GHES_ASSIST && in is_ghes_assist_struct()
129 related_source_id == mces.dmc->header.source_id) in is_ghes_assist_struct()
/linux/Documentation/devicetree/bindings/perf/
H A Damlogic,g12-ddr-pmu.yaml27 - description: DMC bandwidth register space.
28 - description: DMC PLL register space.
/linux/drivers/edac/
H A Ddmc520_edac.c4 * EDAC driver for DMC-520 memory controller.
25 /* DMC-520 registers */
43 /* DMC-520 types, masks and bitfields */
630 { .compatible = "arm,dmc-520", },
651 MODULE_DESCRIPTION("DMC-520 ECC driver");
/linux/drivers/perf/
H A DKconfig209 in the DDR4 Memory Controller (DMC).
227 tristate "Enable PMU support for the ARM DMC-620 memory controller"
230 Support for PMU events monitoring on the ARM DMC-620 memory
H A Dthunderx2_pmu.c13 /* Each ThunderX2(TX2) Socket has a L3C and DMC UNCORE PMU device.
60 /* DMC event IDs */
87 * Each socket has 3 uncore devices associated with a PMU. The DMC and
493 /* DMC event data_transfers granularity is 16 Bytes, convert it to 64 */ in tx2_uncore_event_update()
498 /* L3C and DMC has 16 and 8 interleave channels respectively. in tx2_uncore_event_update()
/linux/Documentation/gpu/
H A Di915.rst198 DMC Firmware Support
202 :doc: DMC Firmware Support
207 DMC wakelock support
211 :doc: DMC wakelock support
496 display microcontroller (DMC). The driver is responsible for loading the
498 to WOPCM using the DMA engine, while the DMC firmware is written through MMIO.
570 DMC section in Microcontrollers
572 See `DMC Firmware Support`_
/linux/drivers/devfreq/
H A DKconfig133 tristate "ARM RK3399 DMC DEVFREQ Driver"
140 This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210.dtsi500 dmc0: dmc@f0000000 {
501 compatible = "samsung,s5pv210-dmc";
505 dmc1: dmc@f1400000 {
506 compatible = "samsung,s5pv210-dmc";

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