| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | qcom_hidma_mgmt.txt | 3 Qualcomm Technologies HIDMA is a high speed DMA device. It only supports
7 Each HIDMA HW instance consists of multiple DMA channels. These channels
14 instance can use like maximum read/write request and number of bytes to
15 read/write in a single burst.
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
31 - max-write-transactions: This value is how many times a write burst is
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| H A D | k3dma.txt | 1 * Hisilicon K3 DMA controller
3 See dma.txt first
6 - compatible: Must be one of
7 - "hisilicon,k3-dma-1.0"
8 - "hisilicon,hisi-pcm-asp-dma-1.0"
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain one interrupt shared by all channel
11 - #dma-cells: see dma.txt, should be 1, para number
12 - dma-channels: physical channels supported
13 - dma-requests: virtual channels supported, each virtual channel
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| H A D | intel,ldma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/intel,ldma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lightning Mountain centralized DMA controllers.
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
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| H A D | renesas,nbpfaxi.txt | 1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
3 * DMA controller
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
29 - max-burst-mem-write: limit burst size for memory writes
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
51 #dma-cells = <2>;
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| H A D | sirfsoc-dma.txt | 1 * CSR SiRFSoC DMA controller
3 See dma.txt first
6 - compatible: Should be "sirf,prima2-dmac", "sirf,atlas7-dmac" or
7 "sirf,atlas7-dmac-v2"
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Should contain one interrupt shared by all channel
10 - #dma-cells: must be <1>. used to represent the number of integer
12 - clocks: clock required
17 dmac0: dma-controller@b00b0000 {
18 compatible = "sirf,prima2-dmac";
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| /freebsd/sys/dev/sound/pci/ |
| H A D | envy24.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 /* -------------------------------------------------------------------- */
39 #define PCIR_DS 0x18 /* DMA Path Registers I/O Base Address */
40 #define PCIR_MT 0x1c /* Professional Multi-Track I/O Base Address */
44 #define PCIM_LAC_SBDMA0 0x0000 /* SB DMA Channel Select: 0 */
45 #define PCIM_LAC_SBDMA1 0x0040 /* SB DMA Channel Select: 1 */
46 #define PCIM_LAC_SBDMA3 0x00c0 /* SB DMA Channel Select: 3 */
48 #define PCIM_LAC_MPU401 0x0008 /* MPU-401 I/O enable */
55 #define PCIM_LCC_SVIDRW 0x0080 /* SVID read/write enable */
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| /freebsd/sys/contrib/device-tree/Bindings/gpu/host1x/ |
| H A D | nvidia,tegra210-nvenc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvenc@[0-9a-f]*$"
24 - nvidia,tegra210-nvenc
25 - nvidia,tegra186-nvenc
26 - nvidia,tegra194-nvenc
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| H A D | nvidia,tegra210-nvdec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra210-nvdec
25 - nvidia,tegra186-nvdec
26 - nvidia,tegra194-nvdec
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| H A D | nvidia,tegra210-nvjpg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvjpg@[0-9a-f]*$"
24 - nvidia,tegra210-nvjpg
25 - nvidia,tegra186-nvjpg
26 - nvidia,tegra194-nvjpg
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| H A D | nvidia,tegra234-nvdec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra234-nvdec
32 clock-names:
34 - const: nvdec
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| /freebsd/contrib/ofed/include/ |
| H A D | udma_barrier.h | 14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
38 /* Barriers for DMA.
40 These barriers are expliclty only for use with user DMA operations. If you
41 are looking for barriers to use with cache-coherent multi-threaded
47 - CPU attached address space (the CPU memory could be a range of things:
48 cached/uncached/non-temporal CPU DRAM, uncached MMIO space in another
51 is not guaranteed to see a write from another CPU then it is also
52 OK for the DMA device to also not see the write after the barrier.
53 - A DMA initiator on a bus. For instance a PCI-E device issuing
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| /freebsd/sys/sys/ |
| H A D | ata.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2000 - 2008 Søren Schmidt <sos@FreeBSD.org>
46 #define ATA_ATAPI_TYPE_CDROM 0x0500 /* CD-ROM device */
79 /*051*/ u_int16_t retired_piomode; /* PIO modes 0-2 */
82 /*052*/ u_int16_t retired_dmamode; /* DMA modes */
86 #define ATA_FLAG_54_58 0x0001 /* words 54-58 valid */
87 #define ATA_FLAG_64_70 0x0002 /* words 64-70 valid */
107 /*063*/ u_int16_t mwdmamodes; /* multiword DMA modes */
110 /*065*/ u_int16_t mwdmamin; /* min. M/W DMA time/word ns */
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| /freebsd/sys/dev/ocs_fc/ |
| H A D | sli4.c | 1 /*-
33 * @defgroup sli SLI-4 Base APIs
38 * All common (i.e. transport-independent) SLI-4 functions are implemented
113 * Although SLI-4 specification defines a common set of registers, their locations
260 const sli4_reg_t *r = &(regmap[reg][sli->if_type]); in sli_reg_read()
262 if ((UINT32_MAX == r->rset) || (UINT32_MAX == r->off)) { in sli_reg_read()
263 ocs_log_err(sli->os, "regname %d not defined for if_type %d\n", reg, sli->if_type); in sli_reg_read()
267 return ocs_reg_read32(sli->os, r->rset, r->off); in sli_reg_read()
271 * @brief Write the value to the given SLI register.
275 * @param val Value to write.
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| H A D | ocs_os.c | 1 /*-
51 return pci_read_config(os->dev, reg, 4); in ocs_config_read32()
57 return pci_read_config(os->dev, reg, 2); in ocs_config_read16()
63 return pci_read_config(os->dev, reg, 1); in ocs_config_read8()
69 return pci_write_config(os->dev, reg, val, 1); in ocs_config_write8()
75 return pci_write_config(os->dev, reg, val, 2); in ocs_config_write16()
81 return pci_write_config(os->dev, reg, val, 4); in ocs_config_write32()
89 * PCI BARs which form a logical address. For example, a 64-bit address uses
103 reg = &ocs->reg[rset]; in ocs_reg_read32()
105 return bus_space_read_4(reg->btag, reg->bhandle, off); in ocs_reg_read32()
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| /freebsd/sys/contrib/dev/iwlwifi/ |
| H A D | iwl-fh.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2021, 2023-2025 Intel Corporation
4 * Copyright (C) 2015-2017 Intel Deutschland GmbH
12 #include "iwl-trans.h"
28 * Keep-Warm (KW) buffer base address.
31 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
33 * from going into a power-savings mode that would cause higher DRAM latency,
34 * and possible data over/under-runs, before all Tx/Rx is complete.
38 * automatically invokes keep-warm accesses when normal accesses might not
42 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
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| /freebsd/sys/contrib/device-tree/Bindings/firmware/ |
| H A D | nvidia,tegra186-bpmp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpm
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| /freebsd/share/man/man4/ |
| H A D | proto.4 | 38 .Bd -ragged -offset indent
45 .Bd -literal -offset indent
51 .Bd -ragged -offset indent
62 Programs can open these device special files and perform register-level
72 Especially hardware diagnostics requires a somewhat user-friendly interface
79 .Xr write 2
86 .Xr write 2
101 whence value of SEEK_SET will target port 0x3fc on the next read or write
111 .Bd -literal
129 .Xr write 2
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| /freebsd/sys/isa/ |
| H A D | pnpreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
46 /* PnP Registers. Write to ADDRESS and then use WRITE/READ_DATA */
69 registers to their power-up values.
71 A write to bit[0] of this register performs a reset function on
76 A write to bit[1] of this register causes all cards to enter the
80 A write to bit[2] of this register causes all cards to reset their
83 This register is write-only. The values are not sticky, that is,
90 A write to this port will cause all cards that have a CSN that
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| /freebsd/sys/dev/ice/ |
| H A D | ice_osdep.c | 1 /* SPDX-License-Identifier: BSD-3-Clause */
54 MALLOC_DEFINE(M_ICE_OSDEP, "ice-osdep", "Intel(R) 100Gb Network Driver osdep allocations");
69 * ice_hw_to_dev - Given a hw private struct, find the associated device_t
84 return sc->dev; in ice_hw_to_dev()
88 * ice_debug - Log a debug message if the type is enabled
93 * Check if hw->debug_mask has enabled the given message type. If so, log the
103 if (!(mask & hw->debug_mask)) in ice_debug()
113 * ice_debug_array - Format and print an array of values to the console
134 if (!(mask & hw->debug_mask)) in ice_debug_array()
140 /* Make sure the row-size isn't too large */ in ice_debug_array()
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| /freebsd/stand/common/ |
| H A D | isapnp.h | 16 * 4. Neither the name of the author nor the names of any co-contributors
50 /* PnP Registers. Write to ADDRESS and then use WRITE/READ_DATA */
70 registers to their power-up values.
72 A write to bit[0] of this register performs a reset function on
77 A write to bit[1] of this register causes all cards to enter the
81 A write to bit[2] of this register causes all cards to reset their
84 This register is write-only. The values are not sticky, that is,
91 A write to this port will cause all cards that have a CSN that
92 matches the write data[7:0] to go from the Sleep state to the either
93 the Isolation state if the write data for this command is zero or
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| /freebsd/sys/powerpc/powermac/ |
| H A D | ata_dbdma.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
31 * Common routines for the DMA engine on both the Apple Kauai and MacIO
49 #include <dev/ata/ata-all.h>
50 #include <dev/ata/ata-pci.h>
58 int write; member
66 struct ata_dbdma_channel *sc = arg->sc; in ata_dbdma_setprd()
71 mtx_lock(&sc->dbdma_mtx); in ata_dbdma_setprd()
73 prev_stop = sc->next_dma_slot-1; in ata_dbdma_setprd()
79 if (sc->next_dma_slot == 0xff) in ata_dbdma_setprd()
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| /freebsd/sys/dev/bhnd/cores/pci/ |
| H A D | bhnd_pcireg.h | 1 /*-
2 * SPDX-License-Identifier: ISC
29 * PCI/PCIe-Gen1 DMA Constants
35 #define BHND_PCIE_DMA32_TRANSLATION 0x80000000 /**< PCIe-Gen1 DMA32 address translation (sb2pcitr…
36 #define BHND_PCIE_DMA32_MASK BHND_PCIE_SBTOPCI2_MASK /**< PCIe-Gen1 DMA32 translation mask */
38 #define BHND_PCIE_DMA64_TRANSLATION _BHND_PCIE_DMA64(TRANSLATION) /**< PCIe-Gen1 DMA64 address tran…
39 #define BHND_PCIE_DMA64_MASK _BHND_PCIE_DMA64(MASK) /**< PCIe-Gen1 DMA64 translation mask */
76 /* BHND_PCI_ARB_CTL - ParkID (>= rev8) */
94 #define BHND_PCI_INTR_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
95 #define BHND_PCI_INTR_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
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| /freebsd/sys/arm/ti/ |
| H A D | ti_sdma.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
56 * Kernel functions for using the DMA controller
59 * DMA TRANSFERS:
60 * A DMA transfer block consists of a number of frames (FN). Each frame
73 * Data structure per DMA channel.
99 * DMA driver context, allocated and stored globally, this driver is not
109 * I guess in theory we should have a mutex per DMA channel for register
133 #define TI_SDMA_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
134 #define TI_SDMA_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
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| /freebsd/sys/contrib/device-tree/Bindings/dma/xilinx/ |
| H A D | xilinx_dma.txt | 6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.0
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| /freebsd/sys/dev/ata/ |
| H A D | ata-lowlevel.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
43 #include <dev/ata/ata-all.h>
44 #include <dev/ata/ata-pci.h>
69 ch->hw.begin_transaction = ata_begin_transaction; in ata_generic_hw()
70 ch->hw.end_transaction = ata_end_transaction; in ata_generic_hw()
71 ch->hw.status = ata_generic_status; in ata_generic_hw()
72 ch->hw.softreset = NULL; in ata_generic_hw()
73 ch->hw.command = ata_generic_command; in ata_generic_hw()
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