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/linux/arch/powerpc/platforms/pseries/
H A Diommu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
21 #include <linux/dma-mapping.h>
33 #include <asm/pci-bridge.h>
37 #include <asm/ppc-pci.h>
66 INIT_LIST_HEAD_RCU(&tbl->it_group_list); in iommu_pseries_alloc_table()
67 kref_init(&tbl->it_kref); in iommu_pseries_alloc_table()
84 table_group->ops = &spapr_tce_table_group_ops; in iommu_pseries_alloc_group()
85 table_group->pgsizes = SZ_4K; in iommu_pseries_alloc_group()
88 table_group->tables[0] = iommu_pseries_alloc_table(node); in iommu_pseries_alloc_group()
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/linux/Documentation/devicetree/bindings/tpm/
H A Dibm,vtpm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nayna Jain <nayna@linux.ibm.com>
23 - IBM,vtpm
24 - IBM,vtpm20
30 - IBM,vtpm
31 - IBM,vtpm20
36 ibm,#dma-address-cells:
39 dma-window properties
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/linux/Documentation/driver-api/
H A Dvme.rst5 -------------------
24 .. code-block:: c
30 if (vdev->id.num >= USER_BUS_MAX)
41 dev->bridge->num.
49 -------------------
53 succeeds, a non-zero value should be returned. A zero return value indicates
61 and/or dma channels (:c:func:`vme_dma_request`). Rather than allowing the device
62 driver to request a specific window or DMA channel (which may be used by a
69 attributes can be requested for a single window, the core will assign a window
71 should be used to identify the allocated resource when it is used. For DMA
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H A Dntb.rst5 NTB (Non-Transparent Bridge) is a type of PCI-Express bridge chip that connects
6 the separate memory systems of two or more computers to the same PCI-Express
9 scratchpad and message registers. Scratchpad registers are read-and-writable
36 ----------------------------------------
40 mainly used to perform the proper memory window initialization. Typically
41 there are two types of memory window interfaces supported by the NTB API:
50 | dma-mapped |-ntb_mw_set_trans(addr) |
52 | (addr) |<======| MW xlat addr |<====| MW base addr |<== memory-mapped IO
53 |------------| |--------------| | |--------------|
55 So typical scenario of the first type memory window initialization looks:
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/linux/drivers/staging/vme_user/
H A Dvme.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include <linux/dma-mapping.h>
51 switch (resource->type) { in find_bridge()
53 return list_entry(resource->entry, struct vme_master_resource, in find_bridge()
54 list)->parent; in find_bridge()
56 return list_entry(resource->entry, struct vme_slave_resource, in find_bridge()
57 list)->parent; in find_bridge()
59 return list_entry(resource->entry, struct vme_dma_resource, in find_bridge()
60 list)->parent; in find_bridge()
62 return list_entry(resource->entry, struct vme_lm_resource, in find_bridge()
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/linux/Documentation/devicetree/bindings/iommu/
H A Diommu.txt13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
18 * Provide system protection against "rogue" DMA by forcing all accesses to go
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
44 the specific IOMMU. Below are a few examples of typical use-cases:
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H A Dnvidia,tegra30-smmu.txt4 - compatible : "nvidia,tegra30-smmu"
5 - reg : Should contain 3 register banks(address and length) for each
7 - interrupts : Should contain MC General interrupt.
8 - nvidia,#asids : # of ASIDs
9 - dma-window : IOVA start address and length.
10 - nvidia,ahb : phandle to the ahb bus connected to SMMU.
14 compatible = "nvidia,tegra30-smmu";
19 dma-window = <0 0x40000000>; /* IOVA start & length */
/linux/Documentation/arch/powerpc/
H A Dpci_iov_resource_on_powernv.rst24 partitions (i.e., filtering of DMA, MSIs etc.) and to provide a mechanism
29 state bits (one for MMIO and one for DMA, they get set together but can be
37 The interesting part is how the various PCIe transactions (MMIO, DMA, ...)
52 For DMA, MSIs and inbound PCIe error messages, we have a table (in
57 - For DMA we then provide an entire address space for each PE that can
59 Each window can be configured to be remapped via a "TCE table" (IOMMU
63 - For MSIs, we have two windows in the address space (one at the top of
64 the 32-bit space and one much higher) which, via a combination of the
70 - Error messages just use the RTT.
76 window and sixteen M64 windows. They have different characteristics.
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/linux/arch/alpha/kernel/
H A Dcore_t2.c1 // SPDX-License-Identifier: GPL-2.0
30 /* For dumping initial DMA window settings. */
33 /* For dumping final DMA window settings. */
37 * By default, we direct-map starting at 2GB, in order to allow the
38 * maximum size direct-map window (2GB) to match the maximum amount of
40 * floppy to DMA only via the scatter/gather window set up for 8MB
41 * ISA DMA, since the maximum ISA DMA address is 2GB-1.
43 * For now, this seems a reasonable trade-off: even though most SABLEs
57 /* The ISA scatter/gather window settings. */
62 * NOTE: Herein lie back-to-back mb instructions. They are magic.
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H A Dcore_cia.c1 // SPDX-License-Identifier: GPL-2.0
34 * NOTE: Herein lie back-to-back mb instructions. They are magic.
58 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
60 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
70 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
72 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
81 * The function number selects which function of a multi-function device
93 u8 bus = bus_dev->number; in mk_conf_addr()
119 *(vip)CIA_IOC_CIA_ERR; /* re-read to force write */ in conf_read()
173 *(vip)CIA_IOC_CIA_ERR; /* re-read to force write */ in conf_write()
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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra186-display.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^display-hub@[0-9a-f]+$"
19 - nvidia,tegra186-display
20 - nvidia,tegra194-display
22 '#address-cells':
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/linux/drivers/crypto/caam/
H A Dpdb.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright 2008-2016 Freescale Semiconductor, Inc.
14 * PDB- IPSec ESP Header Modification Options
19 * Encap and Decap - Decrement TTL (Hop Limit) - Based on the value of the
27 * Decap - DiffServ Copy - Copy the IPv4 TOS or IPv6 Traffic Class byte
32 * Encap- Copy DF bit -if an IPv4 tunnel mode outer IP header is coming from
47 * PDB - IPSec ESP Encap/Decap Options
49 #define PDBOPTS_ESP_ARSNONE 0x00 /* no antireplay window */
50 #define PDBOPTS_ESP_ARS32 0x40 /* 32-entry antireplay window */
51 #define PDBOPTS_ESP_ARS128 0x80 /* 128-entry antireplay window */
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/linux/drivers/iommu/
H A Ddma-iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * A fairly generic DMA-API to IOMMU-API glue layer.
5 * Copyright (C) 2014-2015 ARM Ltd.
7 * based in part on arch/arm/mm/dma-mapping.c:
8 * Copyright (C) 2000-2004 Russell King
15 #include <linux/dma-direct.h>
16 #include <linux/dma-map-ops.h>
20 #include <linux/iommu-dma.h>
35 #include "dma-iommu.h"
36 #include "iommu-pages.h"
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/linux/arch/powerpc/platforms/powernv/
H A Dpci.h1 /* SPDX-License-Identifier: GPL-2.0 */
35 * This is needed because of the behaviour of PCIe-to-PCI bridges. The PHB uses
37 * (and PE) that initiated a DMA. In legacy PCI individual memory read/write
38 * requests aren't tagged with the RID. To work around this the PCIe-to-PCI
41 * PCIe-to-X bridges have a similar issue even though PCI-X requests also have
42 * a RID in the transaction header. The PCIe-to-X bridge is permitted to "take
43 * ownership" of a transaction by a PCI-X device when forwarding it to the PCIe
50 /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
78 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
81 /* 64-bit TCE bypass region */
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/linux/drivers/net/wireless/ath/ath5k/
H A Dpcu.c2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
40 * - Buffering of RX and TX frames (after QCU/DCUs)
42 * - Encrypting and decrypting (using the built-in engine)
44 * - Generating ACKs, RTS/CTS frames
46 * - Maintaining TSF
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/linux/drivers/scsi/csiostor/
H A Dcsio_hw_t5.c4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
42 * Truncation intentional: we only read the bottom 32-bits of the in csio_t5_set_mem_win()
43 * 64-bit BAR0/BAR1 ... We use the hardware backdoor mechanism to in csio_t5_set_mem_win()
46 * accesses to our Configuration Space and we need to set up the PCI-E in csio_t5_set_mem_win()
47 * Memory Window decoders with the actual addresses which will be in csio_t5_set_mem_win()
48 * coming across the PCI-E link. in csio_t5_set_mem_win()
55 * Set up memory window for accessing adapter memory ranges. (Read in csio_t5_set_mem_win()
60 WINDOW_V(ilog2(MEMWIN_APERTURE) - 10), in csio_t5_set_mem_win()
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/linux/Documentation/driver-api/rapidio/
H A Dmport_cdev.rst17 for user-space applications. Most of RapidIO operations are supported through
24 Using available set of ioctl commands user-space applications can perform
27 - Reads and writes from/to configuration registers of mport devices
29 - Reads and writes from/to configuration registers of remote RapidIO devices.
32 - Set RapidIO Destination ID for mport devices (RIO_MPORT_MAINT_HDID_SET)
33 - Set RapidIO Component Tag for mport devices (RIO_MPORT_MAINT_COMPTAG_SET)
34 - Query logical index of mport devices (RIO_MPORT_MAINT_PORT_IDX_GET)
35 - Query capabilities and RapidIO link configuration of mport devices
37 - Enable/Disable reporting of RapidIO doorbell events to user-space applications
39 - Enable/Disable reporting of RIO port-write events to user-space applications
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/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmsi-pic.txt4 - compatible : compatible list, may contain one or two entries
5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
13 - reg : It may contain one or two regions. The first region should contain
19 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
21 be set as edge sensitive. If msi-available-ranges is present, only
25 - msi-available-ranges: use <start count> style section to define which
33 - msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
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/linux/Documentation/userspace-api/media/v4l/
H A Ddev-overlay.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
11 Video overlay devices have the ability to genlock (TV-)video into the
12 (VGA-)video signal of a graphics card, or to store captured images
17 video into a window.
43 advantage of memory mapping and DMA.
62 :ref:`streaming parameter <streaming-par>` ioctls as needed. The
77 privileged because it allows to set up DMA into physical memory,
93 1. Chroma-keying displays the overlaid image only where pixels in the
119 Overlay Window
122 The overlaid image is determined by cropping and overlay window
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/linux/drivers/gpu/drm/imx/lcdc/
H A Dimx-lcdc.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: 2020 Marian Cichy <M.Cichy@pengutronix.de>
22 #include <linux/dma-mapping.h>
39 #define IMX21LCDC_LDCR 0x0030 /* LCDC DMA Control Register */
44 #define IMX21LCDC_LGWSAR 0x0050 /* LCDC Graphic Window Start Address Register */
45 #define IMX21LCDC_LGWSR 0x0054 /* LCDC Graph Window Size Register */
46 #define IMX21LCDC_LGWVPWR 0x0058 /* LCDC Graphic Window Virtual Page Width Register */
47 #define IMX21LCDC_LGWPOR 0x005C /* LCDC Graphic Window Panning Offset Register */
48 #define IMX21LCDC_LGWPR 0x0060 /* LCDC Graphic Window Position Register */
49 #define IMX21LCDC_LGWCR 0x0064 /* LCDC Graphic Window Control Register */
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/linux/sound/mips/
H A Dhal2.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
39 /* 1=DMA Port */
40 /* 9=Global DMA Control */
46 /* If IAR_TYPE_M=DMA Port: */
53 /* If IAR_TYPE_M=Global DMA Control: */
90 /* DMA port enable */
93 #define H2I_DMA_PORT_EN_SY_IN 0x01 /* Synth_in DMA port */
94 #define H2I_DMA_PORT_EN_AESRX 0x02 /* AES receiver DMA port */
95 #define H2I_DMA_PORT_EN_AESTX 0x04 /* AES transmitter DMA port */
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/linux/drivers/staging/rtl8723bs/include/
H A Drtl8723b_spec.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
10 #define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */
59 #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */
87 #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */
190 /* IMR DW0(0x00B0-00B3) Bit 0-31 */
199 #define IMR_BCNDMAINT0_8723B BIT20 /* Beacon DMA Interrupt 0 */
200 #define IMR_BCNDERR0_8723B BIT16 /* Beacon Queue DMA OK0 */
202 #define IMR_BCNDMAINT_E_8723B BIT14 /* Beacon DMA Interrupt Extension for Win7 */
203 #define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */
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/linux/drivers/bus/
H A Dmvebu-mbus.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * - One to configure the access of the CPU to the devices. Depending
13 * each can be use to create a physical memory window that maps to a
17 * - One to configure the access to the CPU to the SDRAM. There are
23 * - Reads out the SDRAM address decoding windows at initialization
30 * devices have to configure those device -> SDRAM windows to ensure
31 * that DMA works properly.
33 * - Provides an API for platform code or device drivers to
34 * dynamically add or remove address decoding windows for the CPU ->
39 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
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/linux/drivers/pci/controller/
H A Dpci-v3-semi.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on the code from arch/arm/mach-integrator/pci_v3.c
8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
128 * during DMA access.
134 /* PCI BASE bits (PCI -> Local Bus) */
141 /* PCI MAP bits (PCI -> Local bus) */
150 /* LB_BASE0,1 bits (Local bus -> PCI) */
172 /* LB_MAP0,1 bits (Local bus -> PCI) */
185 /* LB_BASE2 bits (Local bus -> PCI IO) */
192 /* LB_MAP2 bits (Local bus -> PCI IO) */
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/linux/drivers/gpu/drm/exynos/
H A Dregs-fimc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* drivers/gpu/drm/exynos/regs-fimc.h
18 /* Window offset */
22 /* Window offset 2 */
24 /* Y 1st frame start address for output DMA */
26 /* Y 2nd frame start address for output DMA */
28 /* Y 3rd frame start address for output DMA */
30 /* Y 4th frame start address for output DMA */
32 /* Cb 1st frame start address for output DMA */
34 /* Cb 2nd frame start address for output DMA */
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