Lines Matching +full:dma +full:- +full:window
1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
39 /* 1=DMA Port */
40 /* 9=Global DMA Control */
46 /* If IAR_TYPE_M=DMA Port: */
53 /* If IAR_TYPE_M=Global DMA Control: */
90 /* DMA port enable */
93 #define H2I_DMA_PORT_EN_SY_IN 0x01 /* Synth_in DMA port */
94 #define H2I_DMA_PORT_EN_AESRX 0x02 /* AES receiver DMA port */
95 #define H2I_DMA_PORT_EN_AESTX 0x04 /* AES transmitter DMA port */
96 #define H2I_DMA_PORT_EN_CODECTX 0x08 /* CODEC transmit DMA port */
97 #define H2I_DMA_PORT_EN_CODECR 0x10 /* CODEC receive DMA port */
99 #define H2I_DMA_END 0x9108 /* global dma endian select */
100 #define H2I_DMA_END_SY_IN 0x01 /* Synth_in DMA port */
101 #define H2I_DMA_END_AESRX 0x02 /* AES receiver DMA port */
102 #define H2I_DMA_END_AESTX 0x04 /* AES transmitter DMA port */
103 #define H2I_DMA_END_CODECTX 0x08 /* CODEC transmit DMA port */
104 #define H2I_DMA_END_CODECR 0x10 /* CODEC receive DMA port */
107 #define H2I_DMA_DRV 0x910C /* global PBUS DMA enable */
109 #define H2I_SYNTH_C 0x1104 /* Synth DMA control */
111 #define H2I_AESRX_C 0x1204 /* AES RX dma control */
119 #define H2I_AESTX_C 0x1304 /* AES TX DMA control */
120 #define H2I_AESTX_C_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
127 #define H2I_DAC_C1 0x1404 /* DAC DMA control, 16 bit */
128 #define H2I_DAC_C2 0x1408 /* DAC DMA control, 32 bit */
129 #define H2I_ADC_C1 0x1504 /* ADC DMA control, 16 bit */
130 #define H2I_ADC_C2 0x1508 /* ADC DMA control, 32 bit */
134 #define H2I_C1_DMA_SHIFT 0 /* DMA channel */
136 #define H2I_C1_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
152 #define H2I_C2_R_ATT_SHIFT 18 /* right d/a output - */
154 #define H2I_C2_L_ATT_SHIFT 23 /* left d/a output - */
157 #define H2I_SYNTH_MAP_C 0x1104 /* synth dma handshake ctrl */
177 #define H2I_BRES_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */
208 u32 rx_ud[4]; /* User data window */
213 u32 tx_ud[4]; /* User data window */