Home
last modified time | relevance | path

Searched +full:dma +full:- +full:engine (Results 1 – 25 of 296) sorted by relevance

12345678910>>...12

/freebsd/sys/contrib/device-tree/Bindings/mips/cavium/
H A Ddma-engine.txt1 * DMA Engine.
3 The Octeon DMA Engine transfers between the Boot Bus and main memory.
4 The DMA Engine will be referred to by phandle by any device that is
8 - compatible: "cavium,octeon-5750-bootbus-dma"
12 - reg: The base address of the DMA Engine's register bank.
14 - interrupts: A single interrupt specifier.
17 dma0: dma-engine@1180000000100 {
18 compatible = "cavium,octeon-5750-bootbus-dma";
/freebsd/sys/contrib/device-tree/Bindings/dma/xilinx/
H A Dxilinx_dma.txt1 Xilinx AXI VDMA engine, it does transfers between memory and video devices.
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
14 Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
19 - compatible: Should be one of-
20 "xlnx,axi-vdm
[all...]
H A Dxlnx,zynqmp-dpdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort DMA Controller
10 These bindings describe the DMA engine included in the Xilinx ZynqMP
11 DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
16 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 - $ref: ../dma-controller.yaml#
22 "#dma-cells":
[all …]
H A Dxlnx,zynqmp-dma-1.0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DMA Engine
10 The Xilinx ZynqMP DMA engine supports memory to memory transfers,
12 control and rate control support for slave/peripheral dma access.
15 - Michael Tretter <m.tretter@pengutronix.de>
16 - Harini Katakam <harini.katakam@amd.com>
17 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
[all …]
/freebsd/sys/contrib/device-tree/Bindings/gpu/host1x/
H A Dnvidia,tegra210-nvenc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvenc@[0-9a-f]*$"
24 - nvidia,tegra210-nvenc
25 - nvidia,tegra186-nvenc
26 - nvidia,tegra194-nvenc
[all …]
H A Dnvidia,tegra210-nvdec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra210-nvdec
25 - nvidia,tegra186-nvdec
26 - nvidia,tegra194-nvdec
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/intel/
H A Dintel,hps-copy-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/soc/intel/intel,hps-copy-engin
[all...]
/freebsd/sys/dev/safe/
H A Dsafereg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
33 * Register definitions for SafeNet SafeXcel-1141 crypto device.
37 #define BS_BAR 0x10 /* DMA base address register */
39 #define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */
47 #define SAFE_PE_SRC 0x0004 /* Packet Engine Source */
48 #define SAFE_PE_DST 0x0008 /* Packet Engine Destination */
49 #define SAFE_PE_SA 0x000c /* Packet Engine SA */
50 #define SAFE_PE_LEN 0x0010 /* Packet Engine Length */
51 #define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Ddma-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/dma-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DMA Engine Common Properties
10 - Vinod Koul <vkoul@kernel.org>
13 Generic binding to provide a way for a driver using DMA Engine to
14 retrieve the DMA request or channel information that goes from a
15 hardware device to a DMA controller.
20 "#dma-cells":
[all …]
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml#
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dste-dma40.txt1 * DMA40 DMA Controller
4 - compatible: "stericsson,dma40"
5 - reg: Address range of the DMAC registers
6 - reg-names: Names of the above areas to use during resource look-up
7 - interrupt: Should contain the DMAC interrupt number
8 - #dma-cells: must be <3>
9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
18 dma: dma-controller@801c0000 {
[all …]
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_vcbus.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
58 * Master view" of the address space accessible by the DMA engine. Technically,
61 * that the window must be reconfigured for all channels in a given DMA engine.
62 * The DMA lite engine's window can be configured separately from the 30-bit DMA
63 * engine.
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dmvebu-gated-clock.txt12 -----------------------------------
22 23 crypto CESA (crypto engine)
29 -----------------------------------
45 22 xor0 XOR DMA 0
46 23 xor1 XOR DMA 0
56 -----------------------------------
83 -----------------------------------
97 -----------------------------------
115 22 xor0 XOR DMA 0
116 23 crypto CESA engine
[all …]
/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dcavium-compact-flash.txt8 - compatible: "cavium,ebt3000-compact-flash";
12 - reg: The base address of the CF chip select banks. Depending on
15 - cavium,bus-width: The width of the connection to the CF devices. Valid
18 - cavium,true-ide: Optional, if present the CF connection is in True IDE mode.
20 - cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected
24 compact-flash@5,0 {
25 compatible = "cavium,ebt3000-compact-flash";
27 cavium,bus-width = <16>;
28 cavium,true-ide;
29 cavium,dma-engine-handle = <&dma0>;
/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman_port.h2 * Copyright 2008-2013 Freescale Semiconductor Inc.
154 uint32_t fmbm_rda; /**< Rx DMA attributes*/
160 uint32_t fmbm_rfne; /**< Rx Frame Next Engine*/
162 uint32_t fmbm_rfpne; /**< Rx Frame Parser Next Engine*/
174 uint32_t fmbm_rfene; /**< Rx Frame Enqueue Next Engine */
175 uint32_t reserved0074[0x2]; /**< (0x074-0x07C) */
176 uint32_t fmbm_rcmne; /**< Rx Frame Continuous Mode Next Engine */
179 /**< Buffer Manager pool Information-*/
181 /**< Allocate Counter-*/
183 /**< 0x130/0x140 - 0x15F reserved -*/
[all …]
/freebsd/sys/contrib/device-tree/Bindings/crypto/
H A Darm-cryptocell.txt1 Arm TrustZone CryptoCell cryptographic engine
4 - compatible: Should be one of -
5 "arm,cryptocell-713-ree"
6 "arm,cryptocell-703-ree"
7 "arm,cryptocell-712-ree"
8 "arm,cryptocell-710-ree"
9 "arm,cryptocell-630p-ree"
10 - reg: Base physical address of the engine and length of memory mapped region.
11 - interrupts: Interrupt number for the device.
14 - clocks: Reference to the crypto engine clock.
[all …]
H A Dqcom-qce.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm crypto engine driver
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
19 - const: qcom,crypto-v5.1
23 - const: qcom,crypto-v5.4
27 - items:
28 - enum:
[all …]
H A Dnvidia,tegra234-se-aes.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/nvidia,tegra234-se-aes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Security Engine for AES algorithms
10 The Tegra Security Engine accelerates the following AES encryption/decryption
11 algorithms - AES-ECB, AES-CBC, AES-OFB, AES-XTS, AES-CTR, AES-GCM, AES-CCM,
12 AES-CMAC
15 - Akhil R <akhilrajeev@nvidia.com>
19 const: nvidia,tegra234-se-aes
[all …]
H A Dnvidia,tegra234-se-hash.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/nvidia,tegra234-se-hash.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Security Engine for HASH algorithms
10 The Tegra Security HASH Engine accelerates the following HASH functions -
11 SHA1, SHA224, SHA256, SHA384, SHA512, SHA3-224, SHA3-256, SHA3-384, SHA3-512
15 - Akhil R <akhilrajeev@nvidia.com>
19 const: nvidia,tegra234-se-hash
30 dma-coherent: true
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dqcom,bam-dmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,bam-dmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephan Gerhold <stephan@gerhold.net>
15 or MSM8974. It is built using a simple protocol layer on top of a DMA engine
16 (Qualcomm BAM DMA) and bidirectional interrupts to coordinate power control.
20 DMA engine). As such it is specific to a firmware version, not a particular
25 const: qcom,bam-dmux
32 - description: Power control
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dbrcm,iproc-flexrm-mbox.txt6 FlexRM driver will create a mailbox-controller instance for given FlexRM
10 --------------------
11 - compatible: Should be "brcm,iproc-flexrm-mbox"
12 - reg: Specifies base physical address and size of the FlexRM
14 - msi-parent: Phandles (and potential Device IDs) to MSI controllers
15 The FlexRM engine will send MSIs (instead of wired
17 Refer devicetree/bindings/interrupt-controller/msi.txt
18 - #mbox-cells: Specifies the number of cells needed to encode a mailbox
35 --------------------
36 - dma-coherent: Present if DMA operations made by the FlexRM engine (such
[all …]
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun5i-gr8.dtsi4 * Mylène Josserand <mylene.josserand@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/dma/sun4i-a10.h>
49 #include <dt-bindings/reset/sun5i-ccu.h>
52 display-engine {
53 compatible = "allwinner,sun5i-a13-display-engine";
59 compatible = "allwinner,sun5i-a10s-pwm";
62 #pwm-cells = <3>;
67 #sound-dai-cells = <0>;
[all …]
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dce.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
20 * Copy Engine support: low-level Target-side Copy Engine API.
38 #define CE_DESC_FLAGS_META_DATA_MASK ar->hw_values->ce_desc_meta_data_mask
39 #define CE_DESC_FLAGS_META_DATA_LSB ar->hw_values->ce_desc_meta_data_lsb
92 /* Start of DMA-coherent area reserved for descriptors */
100 * Aligned to descriptor-size boundary.
101 * Points into reserved DMA-coherent area, above.
133 /* Copy Engine settable attributes */
[all …]
/freebsd/share/man/man9/
H A Dbus_dma.980 .Nd Bus and Machine Independent DMA Mapping Interface
163 Direct Memory Access (DMA) is a method of transferring data
165 A DMA transaction can be achieved between device to memory,
170 API is a bus, device, and machine-independent (MI) interface to
179 is used to describe the properties of a group of related DMA
181 One way to view this is that a tag describes the limitations of a DMA engine.
182 For example, if a DMA engine in a device is limited to 32-bit addresses,
188 Some devices may require multiple tags to describe DMA
190 For example, a device might require 16-byte alignment of its descriptor ring
195 If a device has restrictions that are common to all DMA transactions
[all …]
/freebsd/sys/dev/ata/
H A Data-lowlevel.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
43 #include <dev/ata/ata-all.h>
44 #include <dev/ata/ata-pci.h>
69 ch->hw.begin_transaction = ata_begin_transaction; in ata_generic_hw()
70 ch->hw.end_transaction = ata_end_transaction; in ata_generic_hw()
71 ch->hw.status = ata_generic_status; in ata_generic_hw()
72 ch->hw.softreset = NULL; in ata_generic_hw()
73 ch->hw.command = ata_generic_command; in ata_generic_hw()
[all …]

12345678910>>...12