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/freebsd/sys/contrib/device-tree/Bindings/edac/
H A Dsocfpga-eccmgr.txt1 Altera SoCFPGA ECC Manager
2 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
3 The ECC Manager counts and corrects single bit errors and counts/handles
6 Cyclone5 and Arria5 ECC Manager
8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
15 L2 Cache ECC
17 - compatible : Should be "altr,socfpga-l2-ecc"
[all …]
H A Daltr,socfpga-ecc-manager.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/edac/altr,socfpga-ecc-manager.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Altera SoCFPGA ECC Manager
11 - Matthew Gerlach <matthew.gerlach@altera.com>
15 ECC Manager for the Cyclone5, Arria5, Arria10, Stratix10, and Agilex chip
22 - items:
23 - const: altr,socfpga-s10-ecc-manager
24 - const: altr,socfpga-a10-ecc-manager
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dgpmi-nand.txt1 * Freescale General-Purpose Media Interface (GPMI)
7 - compatible : should be "fsl,<chip>-gpmi-nand", chip can be:
13 - reg : should contain registers location and length for gpmi and bch.
14 - reg-names: Should contain the reg names "gpmi-nand" and "bch"
15 - interrupts : BCH interrupt number.
16 - interrupt-names : Should be "bch".
17 - dmas: DMA specifier, consisting of a phandle to DMA controller node
18 and GPMI DMA channel ID.
19 Refer to dma.txt and fsl-mxs-dma.txt for details.
20 - dma-names: Must be "rx-tx".
[all …]
H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
18 is paired with a custom DMA engine (inventively named "Flash DMA") which
27 -- Additional SoC-specific NAND controller properties --
[all …]
H A Dqcom_nandc.txt4 - compatible: must be one of the following:
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
6 SoC and it uses ADM DMA
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
8 IPQ4019 SoC and it uses BAM DMA
9 * "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in
10 IPQ6018 SoC and it uses BAM DMA
11 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
12 IPQ8074 SoC and it uses BAM DMA
13 * "qcom,sdx55-nand" - for QPIC NAND controller v2.0.0 being used in
[all …]
H A Dqcom,nandc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - items:
16 - enum:
17 - qcom,sdx75-nand
18 - const: qcom,sdx55-nand
19 - items:
20 - enum:
[all …]
H A Dst,stm32-fmc2-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/st,stm32-fmc2-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
15 - st,stm32mp15-fmc2
16 - st,stm32mp1-fmc2-nfc
17 - st,stm32mp25-fmc2-nfc
28 - description: tx DMA channel
29 - description: rx DMA channel
[all …]
H A Dmarvell-nand.txt4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
15 - #size-cells: shall be set to 0.
[all …]
H A Dbrcm,brcmnand.txt3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
6 paired with a custom DMA engine (inventively named "Flash DMA") which supports
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
21 string, like "brcm,brcmnand-v7.0"
23 brcm,brcmnand-v2.1
24 brcm,brcmnand-v2.2
25 brcm,brcmnand-v4.0
26 brcm,brcmnand-v5.0
[all …]
H A Dtango-nand.txt5 - compatible: "sigma,smp8758-nand"
6 - reg: address/size of nfc_reg, nfc_mem, and pbus_reg
7 - dmas: reference to the DMA channel used by the controller
8 - dma-names: "rxtx"
9 - clocks: reference to the system clock
10 - #address-cells: <1>
11 - #size-cells: <0>
14 See Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.
18 nandc: nand-controller@2c000 {
19 compatible = "sigma,smp8758-nand";
[all …]
H A Dmarvell,nand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/marvell,nand-controlle
[all...]
H A Dgpmc-nand.txt7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
10 For NAND specific properties such as ECC modes or bus width, please refer to
11 Documentation/devicetree/bindings/mtd/nand-controller.yaml
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
19 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
23 - nand-bus-width: Set this numeric value to 16 if the hardware
27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
28 "sw" 1-bit Hamming ecc code via software
[all …]
H A Dloongson,ls1b-nand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/loongson,ls1b-nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-1 NAND Controller
10 - Keguang Zhang <keguang.zhang@gmail.com>
13 The Loongson-1 NAND controller abstracts all supported operations,
14 meaning it does not support low-level access to raw NAND flash chips.
15 Moreover, the controller is paired with the DMA engine to perform
19 - $ref: nand-controller.yaml
[all …]
H A Dintel,lgm-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: "nand-controller.yaml"
13 - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
17 const: intel,lgm-nand
22 reg-names:
24 - const: ebunand
25 - const: hsnand
[all …]
H A Dti,gpmc-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
20 - enum:
21 - ti,am64-nand
22 - ti,omap2-nand
29 - description: Interrupt for fifoevent
[all …]
H A Dallwinner,sun4i-a10-nand.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: nand-controller.yaml
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
19 - allwinner,sun4i-a10-nand
20 - allwinner,sun8i-a23-nand-controller
29 - description: Bus Clock
[all …]
H A Dgpmi-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale General-Purpose Media Interface (GPMI)
10 - Han Xu <han.xu@nxp.com>
14 flash chips. The device tree may optionally contain sub-nodes
21 - enum:
22 - fsl,imx23-gpmi-nand
23 - fsl,imx28-gpmi-nand
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dqcom,spi-qpic-snand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Md sadre Alam <quic_mdalam@quicinc.com>
13 The QCOM QPIC-SPI-NAND flash controller is an extended version of
15 and parallel mode. It supports typical SPI-NAND page cache
16 operations in single, dual or quad IO mode with pipelined ECC
17 encoding/decoding using the QPIC ECC HW engine.
20 - $ref: /schemas/spi/spi-controller.yaml#
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman.h50 uint8_t num_backup_pools; /**< Number of BM backup pools -
73 considered for depletion (Note - this
76 will be sent after a single-pool
80 considered for depletion (Note - this
89 @Description Enum for defining port DMA swap mode
100 @Description Enum for defining port DMA cache attributes
138 uint32_t fmfp_fcev[4]; /**< FPM FMan-Controller Event 1-4 0x20-0x2f */
139 uint32_t res0030[4]; /**< res 0x30 - 0x3f */
140 uint32_t fmfp_cee[4]; /**< PM FMan-Controller Event 1-4 0x40-0x4f */
141 uint32_t res0050[4]; /**< res 0x50-0x5f */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91-wb50n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-wb50n.dtsi - Device Tree include file for wb50n cpu module
12 model = "Laird Workgroup Bridge 50N - Atmel SAMA5D";
17 stdout-path = "serial0:115200n8";
38 clock-frequency = <32768>;
42 clock-frequency = <12000000>;
46 atmel,osc-bypass;
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
52 cd-gpios = <&pioC 26 GPIO_ACTIVE_LOW>;
[all …]
H A Dat91-kizbox2-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizbox2_common.dtsi - Device Tree Include file for
6 * Copyright (C) 2014-2018 Overkiz SAS
17 stdout-path = &dbgu;
26 clock-frequency = <32768>;
30 clock-frequency = <12000000>;
34 gpio-keys {
35 compatible = "gpio-keys";
37 button-prog {
41 wakeup-source;
[all …]
H A Dat91-kizbox3_common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizbox3.dts - Device Tree Include file for Overkiz Kizbox 3
12 /dts-v1/;
14 #include "sama5d2-pinfunc.h"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mfd/atmel-flexcom.h>
17 #include <dt-bindings/pinctrl/at91.h>
18 #include <dt-bindings/pwm/pwm.h>
36 stdout-path = "serial1:115200n8";
41 clock-frequency = <32768>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]

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