Lines Matching +full:dma +full:- +full:ecc
50 uint8_t num_backup_pools; /**< Number of BM backup pools -
73 considered for depletion (Note - this
76 will be sent after a single-pool
80 considered for depletion (Note - this
89 @Description Enum for defining port DMA swap mode
100 @Description Enum for defining port DMA cache attributes
138 uint32_t fmfp_fcev[4]; /**< FPM FMan-Controller Event 1-4 0x20-0x2f */
139 uint32_t res0030[4]; /**< res 0x30 - 0x3f */
140 uint32_t fmfp_cee[4]; /**< PM FMan-Controller Event 1-4 0x40-0x4f */
141 uint32_t res0050[4]; /**< res 0x50-0x5f */
150 uint32_t fmfp_drd[16]; /**< FPM Data_Ram Data 0-15 0x80 - 0xbf */
159 uint32_t fmfp_cev[4]; /**< FPM CPU Event 1-4 0xe0-0xef */
160 uint32_t res00f0[4]; /**< res 0xf0-0xff */
161 uint32_t fmfp_ps[64]; /**< FPM Port Status 0x100-0x1ff */
174 uint32_t res0230[116]; /**< res 0x230 - 0x3ff */
175 uint32_t fmfp_ts[128]; /**< 0x400: FPM Task Status 0x400 - 0x5ff */
176 uint32_t res0600[0x400 - 384];
183 uint32_t res000c[5]; /**< 0x0c - 0x1f */
187 uint32_t res002c[5]; /**< 0x2c - 0x3f */
188 uint32_t fmbm_arb[8]; /**< BMI Arbitration 0x40 - 0x5f */
189 uint32_t res0060[12]; /**<0x60 - 0x8f */
190 uint32_t fmbm_dtc[3]; /**< Debug Trap Counter 0x90 - 0x9b */
192 uint32_t fmbm_dcv[3][4]; /**< Debug Compare val 0xa0-0xcf */
193 uint32_t fmbm_dcm[3][4]; /**< Debug Compare Mask 0xd0-0xff */
195 uint32_t fmbm_pp[63]; /**< BMI Port Parameters 0x104 - 0x1ff */
197 uint32_t fmbm_pfs[63]; /**< BMI Port FIFO Size 0x204 - 0x2ff */
199 uint32_t fmbm_spliodn[63]; /**< Port Partition ID 0x304 - 0x3ff */
223 uint32_t res0050[7]; /**< 0x50 - 0x6b */
231 uint32_t res0088[2]; /**< 0x88 - 0x8f */
241 } dbg_traps[3]; /**< 0x90 - 0xef */
242 uint8_t res00f0[0x400 - 0xf0]; /**< 0xf0 - 0x3ff */
246 uint32_t fmdmsr; /**< FM DMA status register 0x00 */
247 uint32_t fmdmmr; /**< FM DMA mode register 0x04 */
248 uint32_t fmdmtr; /**< FM DMA bus threshold register 0x08 */
249 uint32_t fmdmhy; /**< FM DMA bus hysteresis register 0x0c */
250 uint32_t fmdmsetr; /**< FM DMA SOS emergency Threshold Register 0x10 */
251 uint32_t fmdmtah; /**< FM DMA transfer bus address high reg 0x14 */
252 uint32_t fmdmtal; /**< FM DMA transfer bus address low reg 0x18 */
253 uint32_t fmdmtcid; /**< FM DMA transfer bus communication ID reg 0x1c */
254 uint32_t fmdmra; /**< FM DMA bus internal ram address register 0x20 */
255 uint32_t fmdmrd; /**< FM DMA bus internal ram data register 0x24 */
256 uint32_t fmdmwcr; /**< FM DMA CAM watchdog counter value 0x28 */
257 uint32_t fmdmebcr; /**< FM DMA CAM base in MURAM register 0x2c */
258 uint32_t fmdmccqdr; /**< FM DMA CAM and CMD Queue Debug reg 0x30 */
259 uint32_t fmdmccqvr1; /**< FM DMA CAM and CMD Queue Value reg #1 0x34 */
260 uint32_t fmdmccqvr2; /**< FM DMA CAM and CMD Queue Value reg #2 0x38 */
261 uint32_t fmdmcqvr3; /**< FM DMA CMD Queue Value register #3 0x3c */
262 uint32_t fmdmcqvr4; /**< FM DMA CMD Queue Value register #4 0x40 */
263 uint32_t fmdmcqvr5; /**< FM DMA CMD Queue Value register #5 0x44 */
264 uint32_t fmdmsefrc; /**< FM DMA Semaphore Entry Full Reject Cntr 0x48 */
265 uint32_t fmdmsqfrc; /**< FM DMA Semaphore Queue Full Reject Cntr 0x4c */
266 uint32_t fmdmssrc; /**< FM DMA Semaphore SYNC Reject Counter 0x50 */
267 uint32_t fmdmdcr; /**< FM DMA Debug Counter 0x54 */
268 uint32_t fmdmemsr; /**< FM DMA Emergency Smoother Register 0x58 */
270 uint32_t fmdmplr[FMAN_LIODN_TBL / 2]; /**< DMA LIODN regs 0x60-0xdf */
271 uint32_t res00e0[0x400 - 56];
300 E_FMAN_DMA_DBG_CNT_SIGLE_BIT_ECC, /**< Single bit ECC errors */
315 E_FMAN_DMA_ERR_CATASTROPHIC = 0, /**< Catastrophic DMA error */
316 E_FMAN_DMA_ERR_REPORT /**< Reported DMA error */
393 E_FMAN_EX_DMA_BUS_ERROR = 0, /**< DMA bus error. */
394 E_FMAN_EX_DMA_READ_ECC, /**< Read Buffer ECC error */
395 E_FMAN_EX_DMA_SYSTEM_WRITE_ECC, /**< Write Buffer ECC err on sys side */
396 E_FMAN_EX_DMA_FM_WRITE_ECC, /**< Write Buffer ECC error on FM side */
398 E_FMAN_EX_FPM_SINGLE_ECC, /**< Single ECC on FPM. */
399 E_FMAN_EX_FPM_DOUBLE_ECC, /**< Double ECC error on FPM ram access */
400 E_FMAN_EX_QMI_SINGLE_ECC, /**< Single ECC on QMI. */
401 E_FMAN_EX_QMI_DOUBLE_ECC, /**< Double bit ECC occurred on QMI */
403 E_FMAN_EX_BMI_LIST_RAM_ECC, /**< Linked List RAM ECC error */
405 E_FMAN_EX_BMI_STATISTICS_RAM_ECC, /**< Statistics RAM ECC Err Enable */
406 E_FMAN_EX_BMI_DISPATCH_RAM_ECC, /**< Dispatch RAM ECC Error Enable */
407 E_FMAN_EX_IRAM_ECC, /**< Double bit ECC occurred on IRAM*/
408 E_FMAN_EX_MURAM_ECC /**< Double bit ECC occurred on MURAM*/
422 E_FMAN_COUNTERS_SEMAPHOR_ENTRY_FULL_REJECT, /**< DMA full entry cntr */
423 E_FMAN_COUNTERS_SEMAPHOR_QUEUE_FULL_REJECT, /**< DMA full CAM Q cntr */
424 E_FMAN_COUNTERS_SEMAPHOR_SYNC_REJECT /**< DMA sync counter */
431 @Description DMA definitions