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/linux/Documentation/devicetree/bindings/dma/
H A Dmediatek,uart-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Long Cheng <long.cheng@mediatek.com>
13 The MediaTek UART APDMA controller provides DMA capabilities
17 - $ref: dma-controller.yaml#
22 - items:
23 - enum:
24 - mediatek,mt2712-uart-dma
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H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
32 10: Multi-Channel Display Engine MCDE RX
55 33: SPI controller 2
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/linux/drivers/ata/
H A Dpata_pdc202xx_old.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
29 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc2026x_cable_detect()
33 if (cis & (1 << (10 + ap->port_no))) in pdc2026x_cable_detect()
41 iowrite8(tf->command, ap->ioaddr.command_addr); in pdc202xx_exec_command()
47 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc202xx_irq_check()
51 if (ap->port_no) { in pdc202xx_irq_check()
67 * pdc202xx_configure_piomode - set chip PIO timing
79 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc202xx_configure_piomode()
80 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno; in pdc202xx_configure_piomode()
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H A Dpata_optidma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_optidma.c - Opti DMA PATA for new ATA layer
6 * The Opti DMA controllers are related to the older PIO PCI controllers
11 * This driver should support Viper-N+, FireStar, FireStar Plus.
13 * These devices support virtual DMA for read (aka the CS5520). Later
15 * so you have to get this right. We don't support the virtual DMA
18 * Bits that are worth knowing
20 * 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
21 * Virtual DMA registers *move* between rev 0x02 and rev 0x10
45 static int pci_clock; /* 0 = 33 1 = 25 */
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H A Dpata_sc1200.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * TODO: Needs custom DMA cleanup code
10 * linux/drivers/ide/pci/sc1200.c Version 0.91 28-Jan-2003
12 * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
37 * sc1200_clock - PCI clock
40 * in use. We return 0 for 33MHz 1 for 48MHz and 2 for 66Mhz
51 return 0; /* 33 MHz mode */ in sc1200_clock()
54 0/3 is 33Mhz 1 is 48 2 is 66 */ in sc1200_clock()
65 * sc1200_set_piomode - PIO setup
75 /* format0, 33Mhz */ in sc1200_set_piomode()
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H A Dpata_cypress.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_cypress.c - Cypress PATA for new ATA layer
46 MODULE_PARM_DESC(enable_dma, "Enable bus master DMA operations");
49 * cy82c693_set_piomode - set initial PIO mode data
58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in cy82c693_set_piomode()
60 const unsigned long T = 1000000 / 33; in cy82c693_set_piomode()
64 if (ata_timing_compute(adev, adev->pio_mode, &t, T, 1) < 0) { in cy82c693_set_piomode()
69 time_16 = clamp_val(t.recover - 1, 0, 15) | in cy82c693_set_piomode()
70 (clamp_val(t.active - 1, 0, 15) << 4); in cy82c693_set_piomode()
71 time_8 = clamp_val(t.act8b - 1, 0, 15) | in cy82c693_set_piomode()
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H A Dpata_artop.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_artop.c - ARTOP ATA controller driver
9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
11 * driver by Thibaut VARENE <varenet@parisc-linux.org>
34 * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
43 * artop62x0_pre_reset - probe begin
57 struct ata_port *ap = link->ap; in artop62x0_pre_reset()
58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in artop62x0_pre_reset()
60 /* Odd numbered device ids are the units with enable bits. */ in artop62x0_pre_reset()
61 if ((pdev->device & 1) && in artop62x0_pre_reset()
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H A Dpata_cmd64x.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_cmd64x.c - CMD64x PATA for new ATA layer
6 * (C) 2009-2010 Bartlomiej Zolnierkiewicz
21 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
75 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in cmd648_cable_detect()
78 /* Check cable detect bits */ in cmd648_cable_detect()
80 if (r & (1 << ap->port_no)) in cmd648_cable_detect()
86 * cmd64x_set_timing - set PIO and MWDMA timing
96 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in cmd64x_set_timing()
98 const unsigned long T = 1000000 / 33; in cmd64x_set_timing()
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H A Dpata_via.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_via.c - VIA PATA for new ATA layer
4 * (C) 2005-2006 Red Hat Inc
10 * VIA VT82C561 - early design, uses ata_generic currently
11 * VIA VT82C576 - MWDMA, 33Mhz
12 * VIA VT82C586 - MWDMA, 33Mhz
13 * VIA VT82C586a - Added UDMA to 33Mhz
14 * VIA VT82C586b - UDMA33
15 * VIA VT82C596a - Nonfunctional UDMA66
16 * VIA VT82C596b - Working UDMA66
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H A Dpata_serverworks.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_serverworks.c - Serverworks PATA for new ATA layer
11 * Copyright (C) 1998-2000 Michel Aubry
12 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
13 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
20 * supports UDMA mode 2 (33 MB/s)
27 * *** to detect 80-conductor cable presence. ***
62 * oem_cable - Dell/Sun serverworks cable detection
66 * for their interfaces in the top two bits of the subsystem ID.
71 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in oem_cable()
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/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa27x.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "dt-bindings/clock/pxa-clock.h"
11 pdma: dma-controller@40000000 {
12 compatible = "marvell,pdma-1.0";
15 #dma-cells = <2>;
17 #dma-channels = <32>;
18 dma-channels = <32>;
19 #dma-requests = <75>;
20 dma-requests = <75>;
24 pxairq: interrupt-controller@40d00000 {
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/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
28 operating-points-v2 = <&opp_table>;
32 opp_table: opp-table {
33 compatible = "operating-points-v2";
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/linux/arch/sparc/kernel/
H A Dpci_sabre.c1 // SPDX-License-Identifier: GPL-2.0
36 #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
37 #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
38 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
39 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
40 #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */
41 #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */
43 #define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */
47 #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
48 #define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
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/linux/arch/powerpc/include/asm/nohash/32/
H A Dpte-85xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
14 - PRESENT *must* be in the bottom two bits because swap PTEs use
15 the top 30 bits.
19 /* Definitions for FSL Book-E Cores */
44 * We define 2 sets of base prot bits, one for basic pages (ie,
47 * the processor might need it for DMA coherency.
56 #include <asm/pgtable-masks.h>
/linux/drivers/net/ethernet/sun/
H A Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
22 * PCI: 33/66MHz clock
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
45 * DEFAULT: 0x0, SIZE: 5 bits
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
65 * DEFAULT: 0x00000000, SIZE: 29 bits
104 len of non-reassembly pkt
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/linux/Documentation/devicetree/bindings/display/imx/
H A Dfsl,imx-lcdc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sascha Hauer <s.hauer@pengutronix.de>
11 - Pengutronix Kernel Team <kernel@pengutronix.de>
16 - enum:
17 - fsl,imx1-fb
18 - fsl,imx21-fb
19 - items:
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/linux/include/uapi/linux/
H A Dvirtio_config.h49 * Virtio feature bits VIRTIO_TRANSPORT_F_START through
52 * rest are per-device feature bits.
70 * If clear - device has the platform DMA (e.g. IOMMU) bypass quirk feature.
71 * If set - use platform DMA tools to access the memory.
76 #define VIRTIO_F_ACCESS_PLATFORM 33
/linux/drivers/pci/controller/
H A Dpci-ftpci100.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on the out-of-tree OpenWRT patch for Cortina Gemini:
54 /* Bits 31..28 gives INTD..INTA status */
58 /* Bits 25..22 masks INTD..INTA */
74 /* Bits 7..4 reserved */
75 /* Bits 3..0 TRDYW */
80 * Bit 19..16 (4 bits) defines the size per below
98 * The DMA base is set to 0x0 for all memory segments, it reflects the
106 * struct faraday_pci_variant - encodes IP block differences
165 return -EINVAL; in faraday_res_to_memcfg()
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/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-ld11.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 compatible = "socionext,uniphier-ld11";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
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/linux/arch/arm64/include/asm/
H A Dcache.h1 /* SPDX-License-Identifier: GPL-2.0-only */
19 /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
20 #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1))
25 /* Ttypen, bits [2(n - 1) + 34 : 2(n - 1) + 33], for n = 1 to 7 */
26 #define CLIDR_TTYPE_SHIFT(level) (2 * ((level) - 1) + CLIDR_EL1_Ttypen_SHIFT)
29 * Memory returned by kmalloc() may be used for DMA, so we must make
41 #include <linux/kasan-enabled.h>
44 #include <asm/mte-def.h>
64 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
65 * permitted in the I-cache.
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx-address.h7 * Copyright (c) 2003-2009 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
60 /* decode within DMA space */
76 /* send out a single-tick command on the NCB bus */
84 * Octeon-I HW never interprets this X (<39:36> reserved
87 * - 0x0 XXX0 0000 0000 to DRAM Cached
88 * - 0x0 XXX0 0FFF FFFF
90 * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000
91 * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF)
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/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn66xx_regs.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
89 /* 1 register (32-bit) to enable Input queues */
92 /* 1 register (32-bit) to enable Output queues */
95 /* 1 register (32-bit) to determine whether Output queues are in reset. */
98 /* 1 register (32-bit) to determine whether Input queues are in reset. */
103 /* 1 register (32-bit) - instr. size of each input queue. */
106 /* 32 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
109 /* 32 registers for Input Queue Start Addr - SLI_PKT0_INSTR_BADDR */
112 /* 32 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
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/linux/drivers/usb/cdns3/
H A Dcdnsp-gadget.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #include <linux/io-64-nonatomic-lo-hi.h>
19 /* Max number slots - only 1 is allowed. */
43 * struct cdnsp_cap_regs - CDNSP Registers.
46 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
47 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
48 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
49 * @hcc_params: HCCPARAMS - Capability Parameters
50 * @db_off: DBOFF - Doorbell array offset
51 * @run_regs_off: RTSOFF - Runtime register space offset
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/linux/arch/arm/boot/dts/st/
H A Dstm32mp135f-dk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/regulator/st,stm32mp13-regulator.h>
15 #include "stm32mp13-pinctrl.dtsi"
18 model = "STMicroelectronics STM32MP135F-DK Discovery Board";
19 compatible = "st,stm32mp135f-dk", "st,stm32mp135";
[all …]
/linux/drivers/net/wireless/intel/iwlegacy/
H A D4965.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
79 * Acquire il->lock before calling this function !
83 * il4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
84 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
87 * NOTE: Acquire il->lock before calling this function !
181 * The first queue used for block-ack aggregation is #7 (4965 only).
182 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
194 #define IL49_RTC_INST_SIZE (IL49_RTC_INST_UPPER_BOUND - \
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