Lines Matching +full:dma +full:- +full:33 +full:bits

1 /* SPDX-License-Identifier: GPL-2.0-only */
19 /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
20 #define CLIDR_CTYPE_SHIFT(level)	(3 * (level - 1))
25 /* Ttypen, bits [2(n - 1) + 34 : 2(n - 1) + 33], for n = 1 to 7 */
26 #define CLIDR_TTYPE_SHIFT(level)	(2 * ((level) - 1) + CLIDR_EL1_Ttypen_SHIFT)
29  * Memory returned by kmalloc() may be used for DMA, so we must make
41 #include <linux/kasan-enabled.h>
44 #include <asm/mte-def.h>
64  * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
65  * permitted in the I-cache.
90 /* Compress a u64 MPIDR value into 32 bits. */
96 	 * These bits are expected to be RES0. If not, return a value with  in arch_compact_of_hwid()
97 	 * the upper 32 bits set to force the caller to give up on 32 bit  in arch_compact_of_hwid()
110  * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
116  *  0 - dcache clean to PoU is required unless :
118  *  1 - dcache clean to PoU is not required for i-to-d coherence.