Lines Matching +full:dma +full:- +full:33 +full:bits
1 /* SPDX-License-Identifier: GPL-2.0 */
15 #include <linux/io-64-nonatomic-lo-hi.h>
19 /* Max number slots - only 1 is allowed. */
43 * struct cdnsp_cap_regs - CDNSP Registers.
46 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
47 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
48 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
49 * @hcc_params: HCCPARAMS - Capability Parameters
50 * @db_off: DBOFF - Doorbell array offset
51 * @run_regs_off: RTSOFF - Runtime register space offset
63 /* Reserved up to (CAPLENGTH - 0x1C) */
67 /* bits 7:0 - how long is the Capabilities register. */
69 /* bits 31:16 */
72 /* HCSPARAMS1 - hcs_params1 - bitmasks */
73 /* bits 0:7, Max Device Endpoints */
80 /* HCCPARAMS - hcc_params - bitmasks */
81 /* 1: device controller can use 64-bit address pointers. */
83 /* 1: device controller uses 64-byte Device Context structures. */
85 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15. */
92 /* db_off bitmask - bits 0:1 reserved. */
95 /* run_regs_off bitmask - bits 0:4 reserved. */
99 * struct cdnsp_op_regs - Device Controller Operational Registers.
100 * @command: USBCMD - Controller command register.
101 * @status: USBSTS - Controller status register.
105 * @dnctrl: DNCTRL - Device notification control register.
106 * @cmd_ring: CRP - 64-bit Command Ring Pointer.
107 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer.
108 * @config_reg: CONFIG - Configure Register
109 * @port_reg_base: PORTSCn - base address for Port Status and Control
123 /* rsvd: offset 0x20-2F. */
127 /* rsvd: offset 0x3C-3FF. */
137 * struct cdnsp_port_regs - Port Registers.
138 * @portsc: PORTSC - Port Status and Control Register.
139 * @portpmsc: PORTPMSC - Port Power Managements Status and Control Register.
140 * @portli: PORTLI - Port Link Info register.
150 * These bits are Read Only (RO) and should be saved and written to the
152 * These bits are also sticky - meaning they're in the AUX well and they aren't
158 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
159 * bits 5:8 (link state), 25:26 ("wake on" enable state)
164 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
165 * bits 1 (port enable/disable), 17 ( connect changed),
170 /* USBCMD - USB command - bitmasks. */
171 /* Run/Stop, controller execution - do not write unless controller is halted.*/
174 * Reset device controller - resets internal controller state machine and all
178 /* Event Interrupt Enable - a '1' allows interrupts from the controller. */
181 * Device System Error Interrupt Enable - get out-of-band signal for
189 * Enable Wrap Event - '1' means device controller generates an event
195 /* bits 18:31 are reserved (and should be preserved on writes). */
200 /* USBSTS - USB status - bitmasks */
201 /* controller not running - set to 1 when run/stop bit is cleared. */
208 /* event interrupt - clear this prior to clearing any IP flags in IR set.*/
212 /* save state status - '1' means device controller is saving state. */
214 /* restore state status - '1' means controllers is restoring state. */
223 /* CRCR - Command Ring Control Register - cmd_ring bitmasks. */
226 /* stop ring immediately - abort the currently executing command. */
236 /* Command Ring pointer - bit mask for the lower 32 bits. */
239 /* CONFIG - Configure Register - config_reg bitmasks. */
240 /* bits 0:7 - maximum number of device slots enabled. */
245 /* PORTSC - Port Status and Control Register - port_reg_base bitmasks */
253 * Port Link State - bits 5:8
274 * bits 10:13 indicate device speed:
275 * 0 - undefined speed - port hasn't be initialized by a reset yet
276 * 1 - full speed
277 * 2 - Reserved (Low Speed not supported
278 * 3 - high speed
279 * 4 - super speed
280 * 5 - super speed
281 * 6-15 reserved
299 /* Port Link State Write Strobe - set this when changing link state */
305 /* 1: reset change - 1 to 0 transition of PORT_RESET */
308 * port link status change - set on some port link state transitions:
310 * ----------------------------------------------------------------------------
311 * - U3 to Resume Wakeup signaling from a device
312 * - Resume to Recovery to U0 USB 3.0 device resume
313 * - Resume to U0 USB 2.0 device resume
314 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
315 * - U3 to U0 Software resume of USB 2.0 device complete
316 * - U2 to U0 L1 resume of USB 2.1 device complete
317 * - U0 to U0 L1 entry rejection by USB 2.1 device
318 * - U0 to disabled L1 entry error with USB 2.1 device
319 * - Any state to inactive Error on USB 3.0 port
322 /* Port configure error change - port failed to configure its link partner. */
333 /* PORTPMSCUSB3 - Port Power Management Status and Control - bitmasks. */
341 /* PORTPMSCUSB2 - Port Power Management Status and Control - bitmasks. */
361 * struct cdnsp_intr_reg - Interrupt Register Set.
362 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
364 * @irq_control: IMOD - Interrupt Moderation Register.
370 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
386 /* IMAN - Interrupt Management Register - irq_pending bitmasks l. */
389 /* bits 2:31 need to be preserved */
393 /* IMOD - Interrupter Moderation Register - irq_control bitmasks. */
400 /* Counter used to count down the time to the next interrupt - HW use only */
405 /* Preserve bits 16:31 of erst_size. */
410 * Dequeue ERST Segment Index (DESI) - Segment number (or alias)
414 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced. */
420 * @microframe_index: MFINDEX - current microframe number.
441 * @port_reg6: Chicken bits for USB20PPP.
456 /* Extended capability IDs - ID 0 reserved */
501 (readl(&(pdev)->rev_cap->ep_supported) & \
505 * struct cdnsp_rev_cap - controller capabilities.
540 * Bits 0 - 7: Endpoint target.
541 * Bits 8 - 15: RsvdZ.
542 * Bits 16 - 31: Stream ID.
557 * @ctx_size: context data structure size - 64 or 32 bits.
558 * @dma: dma address of the bytes.
562 * memory used for the context (bytes) and dma address of it (dma).
570 dma_addr_t dma; member
581 * Slot Context - This assumes the controller uses 32-byte context
582 * structures. If the controller uses 64-byte contexts, there is an additional
594 /* Bits 20:23 in the Slot Context are the speed for the device. */
601 /* Device speed - values defined by PORTSC Device Speed field - 20:23. */
604 /* Index of the last valid endpoint context in this device context - 27:31. */
607 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
616 /* USB device address - assigned by the controller. */
634 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
641 * Endpoint Context - This assumes the controller uses 32-byte context
642 * structures. If the controller uses 64-byte contexts, there is an additional
651 /* offset 0x14 - 0x1f reserved for controller internal use. */
657 * Endpoint State - bits 0:2:
658 * 0 - disabled
659 * 1 - running
660 * 2 - halted due to halt condition
661 * 3 - stopped
662 * 4 - TRB error
663 * 5-7 - reserved
671 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
673 /* Mult - Max number of burst within an interval, in EP companion desc. */
676 /* bits 10:14 are Max Primary Streams. */
678 /* Interval - period between requests to an endpoint - 125u increments. */
700 /* bit 7 is Device Initiate Disable - for disabling stream selection. */
748 * @stream_ring: 64-bit stream ring address, cycle state, and stream type.
749 * @reserved: offset 0x14 - 0x1f reserved for controller internal use.
756 /* Stream Context Types - bits 3:1 of stream ctx deq ptr. */
772 * @ctx_array_dma: Dma address of Context Stream Array.
800 * struct cdnsp_ep - extended device side representation of USB endpoint.
804 * @number: Endpoint number (1 - 15).
809 * @buffering: Number of on-chip buffers related to endpoint.
810 * @buffering_period; Number of on-chip buffers related to periodic endpoint.
855 * @dev_context_ptr: Array of 64-bit DMA addresses for device contexts.
856 * @dma: DMA address for device contexts structure.
860 dma_addr_t dma; member
865 * @buffer: 64-bit buffer address, or immediate data.
879 /* bits 0:23 */
881 /* Completion Code - only applicable for some types of TRBs */
911 #define COMP_UNDEFINED_ERROR 33
925 * @segment_ptr: 64-bit segment pointer.
939 * struct cdnsp_event_cmd - Command completion event TRB.
952 /* Address device - disable SetAddress. */
955 /* Configure Endpoint - Deconfigure. */
972 /* bits 24:31 are the slot ID. */
976 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB. */
1000 /* Port ID - bits 31:24. */
1006 /* transfer_len bitmasks - bits 0:16. */
1008 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31). */
1016 /* Interrupter Target - which MSI-X vector to target the completion event at. */
1026 /* Cycle bit - indicates TRB ownership by driver or driver.*/
1043 /* 0 - NRDY during data stage, 1 - NRDY during status stage (only control). */
1098 /* Transfer Ring No-op (not for the command ring). */
1122 /* Force Header Command - generate a transaction or link management packet. */
1124 /* No-op Command - not for transfer rings. */
1126 /* TRB IDs 24-31 reserved. */
1132 #define TRB_COMPLETION 33
1137 /* MFINDEX Wrap Event - microframe counter wrapped. */
1139 /* TRB IDs 40-47 reserved. */
1142 /* TRB IDs 49-53 reserved. */
1156 * The command ring is 64-byte aligned, so it must also be greater than 16.
1167 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1168 ((addr) & (TRB_MAX_BUFF_SIZE - 1)))
1171 * struct cdnsp_segment - segment related data.
1174 * @dma: DMA address of current segment.
1175 * @bounce_dma: Bounce buffer DMA address .
1183 dma_addr_t dma; member
1184 /* Max packet sized bounce buffer for td-fragmant alignment */
1192 * struct cdnsp_td - Transfer Descriptor object.
1193 * @td_list: Used for binding TD with ep_ring->td_list.
1200 * @drbl - TD has been added to HW scheduler - only for stream capable
1215 * struct cdnsp_dequeue_state - New dequeue pointer for Transfer Ring.
1239 * struct cdnsp_ring - information describing transfer, command or event ring.
1252 * @stream_active: Stream is active - PRIME packet has been detected.
1258 * @type: Ring type - event, transfer, or command ring.
1259 * @last_td_was_short - TD is short TD.
1285 * struct cdnsp_erst_entry - even ring segment table entry object.
1286 * @seg_addr: 64-bit event ring segment address.
1297 * struct cdnsp_erst - even ring segment table for event ring.
1300 * @erst_dma_addr: DMA address for entries array.
1309 * struct cdnsp_request - extended device side representation of usb_request
1337 * struct cdnsp_port - holds information about detected ports.
1357 * struct cdnsp_device - represent USB device.
1371 * @hcs_params1: Cached register copies of read-only HCSPARAMS1
1372 * @hcc_params: Cached register copies of read-only HCCPARAMS1
1380 * @setup_speed - Speed detected for current SETUP packet.
1398 * @device_pool: DMA pool for allocating input and output context.
1399 * @segment_pool: DMA pool for allocating new segments.
1402 * @usb2_port - Port USB 2.0.
1403 * @usb3_port - Port USB 3.0.
1404 * @active_port - Current selected Port.
1424 /* Cached register copies of read-only CDNSP data */
1465 /* DMA pools */
1485 * Registers with 64-bit address pointers should be written to with
1487 * (ptr[1]) second. controller implementations that do not support 64-bit
1597 * next_request - gets the next request on the given list