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/linux/drivers/mmc/host/
H A Dsdhci-esdhc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 /* pltfm-specific */
89 /* DLL Config 0 Register */
95 /* DLL Config 1 Register */
99 /* DLL Status 0 Register */
H A Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
17 #include "sdhci-pltfm.h"
18 #include "sdhci-xenon.h"
128 /* Offset of DLL Control register */
132 /* DLL Update Enable bit */
209 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); in xenon_alloc_emmc_phy()
211 return -ENOMEM; in xenon_alloc_emmc_phy()
213 priv->phy_params = params; in xenon_alloc_emmc_phy()
214 if (priv->phy_type == EMMC_5_0_PHY) in xenon_alloc_emmc_phy()
[all …]
H A Dloongson2-mmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Loongson-2K MMC/SDIO controller driver
5 * Copyright (C) 2018-2025 Loongson Technology Corporation Limited.
14 #include <linux/dma-mapping.h>
22 #include <linux/mmc/slot-gpio.h>
47 /* EMMC DLL Mode Registers */
48 #define LOONGSON2_MMC_REG_DLLVAL 0xf0 /* DLL Master Lock-value Register */
49 #define LOONGSON2_MMC_REG_DLLCTL 0xf4 /* DLL Control Register */
50 #define LOONGSON2_MMC_REG_DELAY 0xf8 /* DLL Delayed Parameter Register */
154 /* Bitfields of DLL master lock-value register */
[all …]
/linux/arch/arm/mach-omap2/
H A Dsleep34xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Karthik Dasu <karthik-dp@ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
57 * with non-Thumb-2-capable firmware.
86 .arch armv7-a
89 stmfd sp!, {r4 - r11, lr} @ save registers on stack
103 ldmfd sp!, {r4 - r11, pc}
115 * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
121 * - only the minimum set of functions gets copied to internal SRAM at boot
122 * and after wake-up from OFF mode, cf. omap_push_sram_idle. The function
[all …]
/linux/arch/arm/mach-orion5x/
H A Dtsx09-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * QNAP TS-x09 Boards common functions
15 #include "tsx09-common.h"
19 * QNAP TS-x09 specific power off method via UART1-attached PIC
29 pr_info("%s: triggering power-off...\n", __func__); in qnap_tsx09_power_off()
33 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_tsx09_power_off()
40 /* send the power-off command 'A' to PIC */ in qnap_tsx09_power_off()
55 return n - '0'; in qnap_tsx09_parse_hex_nibble()
58 return n - 'A' + 10; in qnap_tsx09_parse_hex_nibble()
61 return n - 'a' + 10; in qnap_tsx09_parse_hex_nibble()
[all …]
/linux/include/linux/ssb/
H A Dssb_driver_gige.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 #define SSB_GIGE_PCICFG 0x0800 /* PCI config space (256 bytes) */
25 #define SSB_GIGE_TMSHIGH_RGMII 0x00010000 /* Have an RGMII PHY-bus */
29 #define SSB_GIGE_TMSLOW_DLLEN 0x01000000 /* Enable DLL controls */
62 return container_of(pdev->bus->ops, struct ssb_gige, pci_ops); in pdev_to_ssb_gige()
69 return (dev ? dev->has_rgmii : 0); in ssb_gige_is_rgmii()
77 return !!(dev->dev->bus->sprom.boardflags_lo & in ssb_gige_have_roboswitch()
87 return ((dev->dev->bus->chip_id == 0x4785) && in ssb_gige_one_dma_at_once()
88 (dev->dev->bus->chip_rev < 2)); in ssb_gige_one_dma_at_once()
97 return (dev->dev->bus->chip_id == 0x4785); in ssb_gige_must_flush_posted_writes()
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/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-spi.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 #include <asm/octeon/cvmx-config.h>
36 #include <asm/octeon/cvmx-pko.h>
37 #include <asm/octeon/cvmx-spi.h>
39 #include <asm/octeon/cvmx-spxx-defs.h>
40 #include <asm/octeon/cvmx-stxx-defs.h>
41 #include <asm/octeon/cvmx-srxx-defs.h>
108 int res = -1; in cvmx_spi_start_interface()
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/linux/drivers/phy/microchip/
H A Dlan966x_serdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/phy/phy-lan966x-serdes.h>
189 lan_rmw(HSIO_SD_CFG_LANE_10BIT_SEL_SET(res_struct->lane_10bit_sel) | in lan966x_sd6g40_reg_cfg()
190 HSIO_SD_CFG_RX_RATE_SET(res_struct->rx_rate) | in lan966x_sd6g40_reg_cfg()
191 HSIO_SD_CFG_TX_RATE_SET(res_struct->tx_rate) | in lan966x_sd6g40_reg_cfg()
192 HSIO_SD_CFG_TX_INVERT_SET(res_struct->tx_invert) | in lan966x_sd6g40_reg_cfg()
193 HSIO_SD_CFG_RX_INVERT_SET(res_struct->rx_invert) | in lan966x_sd6g40_reg_cfg()
194 HSIO_SD_CFG_LANE_LOOPBK_EN_SET(res_struct->lane_loopbk_en) | in lan966x_sd6g40_reg_cfg()
205 macro->ctrl->regs, HSIO_SD_CFG(idx)); in lan966x_sd6g40_reg_cfg()
207 lan_rmw(HSIO_MPLL_CFG_MPLL_MULTIPLIER_SET(res_struct->mpll_multiplier) | in lan966x_sd6g40_reg_cfg()
[all …]
/linux/drivers/tty/serial/
H A Domap-serial.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for OMAP-UART controller.
16 * this driver as required for the omap-platform.
38 #include <linux/platform_data/serial-omap.h>
79 #define OMAP_UART_DMA_CH_FREE -1
136 unsigned char dll; member
176 offset <<= up->port.regshift; in serial_in()
177 return readw(up->port.membase + offset); in serial_in()
182 offset <<= up->port.regshift; in serial_out()
183 writew(value, up->port.membase + offset); in serial_out()
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H A Dsc16is7xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - common code
53 * - only on 75x/76x
56 * - only on 75x/76x
59 * - only on 75x/76x
62 * - only on 75x/76x
90 /* IER register bits - write only if (EFR[4] == 1) */
103 /* FCR register bits - write only if (EFR[4] == 1) */
113 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
115 * - only on 75x/76x
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/linux/drivers/spi/
H A Dspi-cadence-xspi.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (C) 2020-21 Cadence
19 #include <linux/spi/spi-mem.h>
27 #define CDNS_XSPI_NAME "cadence-xspi"
31 * configure XSPI controller pin-strap settings
43 /* PHY DLL slave control register */
46 /* DLL PHY control register */
93 /* Controller config register */
157 FIELD_PREP(CDNS_XSPI_CMD_P1_R1_ADDR0, (op)->addr.val & 0xff))
160 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR1, ((op)->addr.val >> 8) & 0xFF) | \
[all …]
/linux/drivers/net/dsa/microchip/
H A Dlan937x_main.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2024 Microchip Technology Inc.
21 /* marker for ports without built-in PHY */
25 * lan9370_phy_addr - Mapping of LAN9370 switch ports to PHY addresses.
28 * where ports 1-4 are connected to integrated 100BASE-T1 PHYs, and
41 * lan9371_phy_addr - Mapping of LAN9371 switch ports to PHY addresses.
55 * lan9372_phy_addr - Mapping of LAN9372 switch ports to PHY addresses.
71 * lan9373_phy_addr - Mapping of LAN9373 switch ports to PHY addresses.
87 * lan9374_phy_addr - Mapping of LAN9374 switch ports to PHY addresses.
115 * lan937x_create_phy_addr_map - Create port-to-PHY address map for MDIO bus.
[all …]
/linux/drivers/firmware/xilinx/
H A Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2022 Xilinx, Inc.
6 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
14 #include <linux/arm-smccc.h>
28 #include <linux/firmware/xlnx-zynqmp.h>
29 #include <linux/firmware/xlnx-event-manager.h>
30 #include "zynqmp-debug.h"
37 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */
39 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
54 * struct zynqmp_devinfo - Structure for Zynqmp device instance
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm6125.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
16 interrupt-parent = <&intc>;
[all …]
H A Dsdx75.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,sdx75.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom,rpmhpd.h>
[all …]
H A Dqdu1000.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interconnect/qcom,icc.h>
11 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dci_smumgr.c100 return -EINVAL; in ci_set_smc_sram_address()
103 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr); in ci_set_smc_sram_address()
104 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); in ci_set_smc_sram_address()
120 return -EINVAL; in ci_copy_bytes_to_smc()
134 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); in ci_copy_bytes_to_smc()
137 byte_count -= 4; in ci_copy_bytes_to_smc()
151 original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0); in ci_copy_bytes_to_smc()
153 extra_shift = 8 * (4 - byte_count); in ci_copy_bytes_to_smc()
158 byte_count--; in ci_copy_bytes_to_smc()
170 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); in ci_copy_bytes_to_smc()
[all …]
/linux/arch/arm/mach-tegra/
H A Dsleep-tegra30.S1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <asm/asm-offsets.h>
81 .arch armv7-a
192 * Puts the current CPU in wait-for-event mode on the flow controller
193 * and powergates it -- flags (in R0) indicate the request type.
196 * corrupts r0-r4, r10-r12
293 * CPU power-gating process, to avoid loading from SDRAM which
294 * are not supported once SDRAM is put into self-refresh.
296 * disabled before putting SDRAM into self-refresh to avoid
356 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
[all …]
/linux/drivers/mtd/nand/raw/
H A Dcadence-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/dma-mapping.h>
26 * - PIO - can work in master or slave DMA
27 * - CDMA - needs Master DMA for accessing command descriptors.
28 * - Generic mode - can use only slave DMA.
101 * Transfer config 0 register.
111 * Transfer config 1 register.
117 /* Size of not-last data sector. */
161 /* Support for NV-DDR2/3 work mode. */
163 /* Support for NV-DDR work mode. */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramgt215.c120 hi--; in gt215_link_train_calc()
125 median[i] = ((hi - lo) >> 1) + lo; in gt215_link_train_calc()
138 train->r_100720 = 0; in gt215_link_train_calc()
143 train->r_100720 |= ((median[i] & 0x0f) << (i << 2)); in gt215_link_train_calc()
146 train->r_1111e0 = 0x02000000 | (bin * 0x101); in gt215_link_train_calc()
147 train->r_111400 = 0x0; in gt215_link_train_calc()
156 struct gt215_ltrain *train = &ram->ltrain; in gt215_link_train()
157 struct gt215_ramfuc *fuc = &ram->fuc; in gt215_link_train()
158 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in gt215_link_train()
159 struct nvkm_device *device = subdev->device; in gt215_link_train()
[all …]
/linux/drivers/video/fbdev/aty/
H A Dradeon_pm.c1 // SPDX-License-Identifier: GPL-2.0
10 * some D2-state (APM-style) sleep/wakeup code for use on some PowerMacs,
11 * and the necessary bits to re-initialize from scratch a few chips found
32 * - enable D2 sleep in some IBM Thinkpads
33 * - special case for Samsung P35
102 for (id = radeon_workaround_list; id->ident != NULL; id++ ) in radeon_apply_workarounds()
103 if ((id->subsystem_vendor == rinfo->pdev->subsystem_vendor ) && in radeon_apply_workarounds()
104 (id->subsystem_device == rinfo->pdev->subsystem_device )) { in radeon_apply_workarounds()
108 ", enabling workaround\n", id->ident); in radeon_apply_workarounds()
110 rinfo->pm_mode |= id->pm_mode_modifier; in radeon_apply_workarounds()
[all …]
/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
815 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
[all …]
/linux/drivers/usb/serial/
H A Dio_usbvend.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * USBVEND.H Vendor-specific USB definitions
7 * must be kept backward-compatible with older firmware.
34 // We break the USB-defined PID into an OEM Id field (upper 6 bits)
40 // ION-device OEM IDs
50 // ION-device Device IDs
51 // Product IDs - assigned to match middle digit of serial number (No longer true)
77 // ION_DEVICE_ID_EDGEPORT_8_HANDBUILT 0x009 // Hand-built Edgeport/8 (Placeholder, used in middle d…
83 #define ION_DEVICE_ID_EDGEPORT_8 0x00F // Edgeport/8 (single-CPU)
88 #define ION_DEVICE_ID_EDGEPORT_8I 0x014 // Edgeport/8 RS422 (single-CPU)
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/linux/drivers/net/dsa/
H A Dmt7530.c1 // SPDX-License-Identifier: GPL-2.0-only
49 if (priv->bus) in mt7530_mutex_lock()
50 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_mutex_lock()
56 if (priv->bus) in mt7530_mutex_unlock()
57 mutex_unlock(&priv->bus->mdio_lock); in mt7530_mutex_unlock()
63 struct mii_bus *bus = priv->bus; in core_write()
69 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
75 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
81 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
87 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
[all …]

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