Lines Matching +full:dll +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0-only
6 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
33 * "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de>
57 * "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de>
79 * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
109 unsigned int pixclock = var->pixclock;
114 mt->pixclock = 1000000000 / pixclock;
115 if (mt->pixclock < 1) mt->pixclock = 1;
116 mt->mnp = -1;
117 mt->dblscan = var->vmode & FB_VMODE_DOUBLE;
118 mt->interlaced = var->vmode & FB_VMODE_INTERLACED;
119 mt->HDisplay = var->xres;
120 mt->HSyncStart = mt->HDisplay + var->right_margin;
121 mt->HSyncEnd = mt->HSyncStart + var->hsync_len;
122 mt->HTotal = mt->HSyncEnd + var->left_margin;
123 mt->VDisplay = var->yres;
124 mt->VSyncStart = mt->VDisplay + var->lower_margin;
125 mt->VSyncEnd = mt->VSyncStart + var->vsync_len;
126 mt->VTotal = mt->VSyncEnd + var->upper_margin;
127 mt->sync = var->sync;
134 unsigned int fxtal = pll->ref_freq;
143 printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max);
144 printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq);
146 printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min);
147 printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min);
148 printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max);
149 printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min);
150 printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max);
153 for (p = 1; p <= pll->post_shift_max; p++) {
158 if (fwant < pll->vco_freq_min) fwant = pll->vco_freq_min;
160 for (; p-- > 0; fwant >>= 1, bestdiff >>= 1) {
163 if (fwant < pll->vco_freq_min) break;
164 for (m = pll->in_div_min; m <= pll->in_div_max; m++) {
168 n = (fwant * (m + 1) + (fxtal >> 1)) / fxtal - 1;
169 if (n > pll->feed_div_max)
171 if (n < pll->feed_div_min)
172 n = pll->feed_div_min;
175 diff = fwant - fvco;
177 diff = fvco - fwant;
198 struct matrox_hw_state * const hw = &minfo->hw;
202 hw->SEQ[0] = 0x00;
203 hw->SEQ[1] = 0x01; /* or 0x09 */
204 hw->SEQ[2] = 0x0F; /* bitplanes */
205 hw->SEQ[3] = 0x00;
206 hw->SEQ[4] = 0x0E;
208 if (m->dblscan) {
209 m->VTotal <<= 1;
210 m->VDisplay <<= 1;
211 m->VSyncStart <<= 1;
212 m->VSyncEnd <<= 1;
214 if (m->interlaced) {
215 m->VTotal >>= 1;
216 m->VDisplay >>= 1;
217 m->VSyncStart >>= 1;
218 m->VSyncEnd >>= 1;
222 hw->GCTL[0] = 0x00;
223 hw->GCTL[1] = 0x00;
224 hw->GCTL[2] = 0x00;
225 hw->GCTL[3] = 0x00;
226 hw->GCTL[4] = 0x00;
227 hw->GCTL[5] = 0x40;
228 hw->GCTL[6] = 0x05;
229 hw->GCTL[7] = 0x0F;
230 hw->GCTL[8] = 0xFF;
234 hw->ATTR[i] = i;
235 hw->ATTR[16] = 0x41;
236 hw->ATTR[17] = 0xFF;
237 hw->ATTR[18] = 0x0F;
238 hw->ATTR[19] = 0x00;
239 hw->ATTR[20] = 0x00;
241 hd = m->HDisplay >> 3;
242 hs = m->HSyncStart >> 3;
243 he = m->HSyncEnd >> 3;
244 ht = m->HTotal >> 3;
248 divider = minfo->curr.final_bppShift;
265 hd = hd - 1;
266 hs = hs - 1;
267 he = he - 1;
268 ht = ht - 1;
269 vd = m->VDisplay - 1;
270 vs = m->VSyncStart - 1;
271 ve = m->VSyncEnd - 1;
272 vt = m->VTotal - 2;
278 wd = minfo->fbcon.var.xres_virtual * minfo->curr.final_bppShift / 64;
280 hw->CRTCEXT[0] = 0;
281 hw->CRTCEXT[5] = 0;
282 if (m->interlaced) {
283 hw->CRTCEXT[0] = 0x80;
284 hw->CRTCEXT[5] = (hs + he - ht) >> 1;
285 if (!m->dblscan)
289 hw->CRTCEXT[0] |= (wd & 0x300) >> 4;
290 hw->CRTCEXT[1] = (((ht - 4) & 0x100) >> 8) |
294 /* FIXME: Enable vidrst only on G400, and only if TV-out is used */
295 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1)
296 hw->CRTCEXT[1] |= 0x88; /* enable horizontal and vertical vidrst */
297 hw->CRTCEXT[2] = ((vt & 0xC00) >> 10) |
302 hw->CRTCEXT[3] = (divider - 1) | 0x80;
303 hw->CRTCEXT[4] = 0;
305 hw->CRTC[0] = ht-4;
306 hw->CRTC[1] = hd;
307 hw->CRTC[2] = hd;
308 hw->CRTC[3] = (hbe & 0x1F) | 0x80;
309 hw->CRTC[4] = hs;
310 hw->CRTC[5] = ((hbe & 0x20) << 2) | (he & 0x1F);
311 hw->CRTC[6] = vt & 0xFF;
312 hw->CRTC[7] = ((vt & 0x100) >> 8) |
320 hw->CRTC[8] = 0x00;
321 hw->CRTC[9] = ((vd & 0x200) >> 4) |
323 if (m->dblscan && !m->interlaced)
324 hw->CRTC[9] |= 0x80;
326 hw->CRTC[i] = 0x00;
327 hw->CRTC[16] = vs /* & 0xFF */;
328 hw->CRTC[17] = (ve & 0x0F) | 0x20;
329 hw->CRTC[18] = vd /* & 0xFF */;
330 hw->CRTC[19] = wd /* & 0xFF */;
331 hw->CRTC[20] = 0x00;
332 hw->CRTC[21] = vd /* & 0xFF */;
333 hw->CRTC[22] = (vt + 1) /* & 0xFF */;
334 hw->CRTC[23] = 0xC3;
335 hw->CRTC[24] = lc;
342 struct matrox_hw_state * const hw = &minfo->hw;
347 dprintk(KERN_INFO "MiscOutReg: %02X\n", hw->MiscOutReg);
350 dprintk("%02X:", hw->SEQ[i]);
354 dprintk("%02X:", hw->GCTL[i]);
358 dprintk("%02X:", hw->CRTC[i]);
362 dprintk("%02X:", hw->ATTR[i]);
369 mga_outb(M_MISC_REG, hw->MiscOutReg);
371 mga_setr(M_SEQ_INDEX, i, hw->SEQ[i]);
372 mga_setr(M_CRTC_INDEX, 17, hw->CRTC[17] & 0x7F);
374 mga_setr(M_CRTC_INDEX, i, hw->CRTC[i]);
376 mga_setr(M_GRAPHICS_INDEX, i, hw->GCTL[i]);
380 mga_outb(M_ATTR_INDEX, hw->ATTR[i]);
385 mga_outb(M_DAC_VAL, hw->DACpal[i]);
399 unsigned char* dst = bd->pins;
414 bd->pins_len = pins_len;
417 unsigned char* dst = bd->pins;
424 bd->pins_len = 0x40;
440 bd->version.vMaj = (h >> 4) & 0xF;
441 bd->version.vMin = h & 0xF;
442 bd->version.vRev = readb(vbios + pcir_offset + 0x13);
447 bd->version.vMaj = (h >> 4) & 0xF;
448 bd->version.vMin = h & 0xF;
449 bd->version.vRev = 0;
460 bd->output.state = b;
466 /* Check for 'IBM .*(V....TVO' string - it means TVO BIOS */
467 bd->output.tvout = 0;
481 bd->output.tvout = 1;
496 bd->bios_valid = 1;
536 switch (bd->pins[22]) {
541 if (get_unaligned_le16(bd->pins + 24)) {
542 maxdac = get_unaligned_le16(bd->pins + 24) * 10;
544 minfo->limits.pixel.vcomax = maxdac;
545 minfo->values.pll.system = get_unaligned_le16(bd->pins + 28) ?
546 get_unaligned_le16(bd->pins + 28) * 10 : 50000;
548 minfo->features.pll.ref_freq = 14318;
549 minfo->values.reg.mctlwtst = 0x00030101;
556 minfo->limits.pixel.vcomax = 220000;
557 minfo->values.pll.system = 50000;
558 minfo->features.pll.ref_freq = 14318;
559 minfo->values.reg.mctlwtst = 0x00030101;
565 minfo->limits.pixel.vcomax =
566 minfo->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000);
567 minfo->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) |
568 ((bd->pins[51] & 0x02) ? 0x00000100 : 0) |
569 ((bd->pins[51] & 0x04) ? 0x00010000 : 0) |
570 ((bd->pins[51] & 0x08) ? 0x00020000 : 0);
571 minfo->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
572 minfo->features.pll.ref_freq = 14318;
579 minfo->limits.pixel.vcomax =
580 minfo->limits.system.vcomax = 230000;
581 minfo->values.reg.mctlwtst = 0x00030101;
582 minfo->values.pll.system = 50000;
583 minfo->features.pll.ref_freq = 14318;
589 minfo->limits.pixel.vcomax =
590 minfo->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000);
591 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ?
592 0x01250A21 : get_unaligned_le32(bd->pins + 48);
593 /* memory config */
594 minfo->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) |
595 ((bd->pins[57] << 22) & 0x00C00000) |
596 ((bd->pins[56] << 1) & 0x000001E0) |
597 ( bd->pins[56] & 0x0000000F);
598 minfo->values.reg.opt = (bd->pins[54] & 7) << 10;
599 minfo->values.reg.opt2 = bd->pins[58] << 12;
600 minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000;
607 minfo->limits.pixel.vcomax =
608 minfo->limits.system.vcomax = 230000;
609 minfo->values.reg.mctlwtst = 0x01250A21;
610 minfo->values.reg.memrdbk = 0x00000000;
611 minfo->values.reg.opt = 0x00000C00;
612 minfo->values.reg.opt2 = 0x00000000;
613 minfo->features.pll.ref_freq = 27000;
619 minfo->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000;
620 minfo->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 38] * 4000;
621 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71);
622 minfo->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) |
623 ((bd->pins[87] << 22) & 0x00C00000) |
624 ((bd->pins[86] << 1) & 0x000001E0) |
625 ( bd->pins[86] & 0x0000000F);
626 minfo->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) |
627 ((bd->pins[53] << 22) & 0x10000000) |
628 ((bd->pins[53] << 7) & 0x00001C00);
629 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 67);
630 minfo->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000;
631 minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000;
638 minfo->limits.pixel.vcomax =
639 minfo->limits.system.vcomax = 252000;
640 minfo->values.reg.mctlwtst = 0x04A450A1;
641 minfo->values.reg.memrdbk = 0x000000E7;
642 minfo->values.reg.opt = 0x10000400;
643 minfo->values.reg.opt3 = 0x0190A419;
644 minfo->values.pll.system = 200000;
645 minfo->features.pll.ref_freq = 27000;
653 mult = bd->pins[4]?8000:6000;
655 minfo->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult;
656 minfo->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 36] * mult;
657 minfo->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? minfo->limits.system.vcomax : bd->pins[ 37] * mult;
658 minfo->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult;
659 minfo->limits.system.vcomin = (bd->pins[121] == 0xFF) ? minfo->limits.pixel.vcomin : bd->pins[121] * mult;
660 minfo->limits.video.vcomin = (bd->pins[122] == 0xFF) ? minfo->limits.system.vcomin : bd->pins[122] * mult;
661 minfo->values.pll.system =
662 minfo->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000;
663 minfo->values.reg.opt = get_unaligned_le32(bd->pins + 48);
664 minfo->values.reg.opt2 = get_unaligned_le32(bd->pins + 52);
665 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 94);
666 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98);
667 minfo->values.reg.memmisc = get_unaligned_le32(bd->pins + 102);
668 minfo->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106);
669 minfo->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000;
670 minfo->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20;
671 minfo->values.memory.dll = (bd->pins[115] & 0x02) != 0;
672 minfo->values.memory.emrswen = (bd->pins[115] & 0x01) != 0;
673 minfo->values.reg.maccess = minfo->values.memory.emrswen ? 0x00004000 : 0x00000000;
674 if (bd->pins[115] & 4) {
675 minfo->values.reg.mctlwtst_core = minfo->values.reg.mctlwtst;
681 minfo->values.reg.mctlwtst_core = (minfo->values.reg.mctlwtst & ~7) |
682 wtst_xlat[minfo->values.reg.mctlwtst & 7];
684 minfo->max_pixel_clock_panellink = bd->pins[47] * 4000;
691 minfo->limits.pixel.vcomax =
692 minfo->limits.system.vcomax =
693 minfo->limits.video.vcomax = 600000;
694 minfo->limits.pixel.vcomin =
695 minfo->limits.system.vcomin =
696 minfo->limits.video.vcomin = 256000;
697 minfo->values.pll.system =
698 minfo->values.pll.video = 284000;
699 minfo->values.reg.opt = 0x404A1160;
700 minfo->values.reg.opt2 = 0x0000AC00;
701 minfo->values.reg.opt3 = 0x0090A409;
702 minfo->values.reg.mctlwtst_core =
703 minfo->values.reg.mctlwtst = 0x0C81462B;
704 minfo->values.reg.memmisc = 0x80000004;
705 minfo->values.reg.memrdbk = 0x01001103;
706 minfo->features.pll.ref_freq = 27000;
707 minfo->values.memory.ddr = 1;
708 minfo->values.memory.dll = 1;
709 minfo->values.memory.emrswen = 1;
710 minfo->values.reg.maccess = 0x00004000;
719 switch (minfo->chip) {
730 if (!bd->bios_valid) {
732 return -1;
734 if (bd->pins_len < 64) {
736 return -1;
738 if (bd->pins[0] == 0x2E && bd->pins[1] == 0x41) {
739 pins_version = bd->pins[5];
742 return -1;
747 if (bd->pins_len != pinslen[pins_version - 1]) {
749 return -1;
764 return -1;
773 struct pci_dev *pdev = minfo->pcidev;
775 memset(&minfo->bios, 0, sizeof(minfo->bios));
779 pci_read_config_dword(pdev, minfo->devflags.fbResource, &fbbase);
781 parse_bios(vaddr_va(minfo->video.vbase), &minfo->bios);
785 if (!minfo->bios.bios_valid) {
795 if (ven != pdev->vendor || dev != pdev->device) {
797 ven, dev, pdev->vendor, pdev->device);
799 parse_bios(b, &minfo->bios);
805 matroxfb_set_limits(minfo, &minfo->bios);
807 (minfo->values.reg.opt & 0x1C00) >> 10);
818 MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <vandrove@vc.cvut.cz>");