1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) 2019-2024 Microchip Technology Inc.
21 /* marker for ports without built-in PHY */
25  * lan9370_phy_addr - Mapping of LAN9370 switch ports to PHY addresses.
28  * where ports 1-4 are connected to integrated 100BASE-T1 PHYs, and
41  * lan9371_phy_addr - Mapping of LAN9371 switch ports to PHY addresses.
55  * lan9372_phy_addr - Mapping of LAN9372 switch ports to PHY addresses.
71  * lan9373_phy_addr - Mapping of LAN9373 switch ports to PHY addresses.
87  * lan9374_phy_addr - Mapping of LAN9374 switch ports to PHY addresses.
115  * lan937x_create_phy_addr_map - Create port-to-PHY address map for MDIO bus.
121  * 1. **SPI Access**: A straightforward one-to-one port-to-PHY address
127  *    https://microchip.my.site.com/s/article/LAN9374-Virtual-PHY-PHY-Address-Mapping
150 		for (i = 0; i < dev->info->port_cnt; i++)  in lan937x_create_phy_addr_map()
151 			dev->phy_addr_map[i] = i;  in lan937x_create_phy_addr_map()
169 	switch (dev->info->chip_id) {  in lan937x_create_phy_addr_map()
191 		return -EINVAL;  in lan937x_create_phy_addr_map()
194 	if (size < dev->info->port_cnt)  in lan937x_create_phy_addr_map()
195 		return -EINVAL;  in lan937x_create_phy_addr_map()
197 	for (i = 0; i < dev->info->port_cnt; i++) {  in lan937x_create_phy_addr_map()
199 			dev->phy_addr_map[i] = phy_addr_map[i];  in lan937x_create_phy_addr_map()
201 			dev->phy_addr_map[i] = phy_addr_map[i] + offset;  in lan937x_create_phy_addr_map()
208  * lan937x_mdio_bus_preinit - Pre-initialize MDIO bus for accessing PHYs.
249 		dev_err(dev->dev, "failed to preinit the MDIO bus\n");  in lan937x_mdio_bus_preinit()
275 	if (!dev->info->internal_phy[addr])  in lan937x_internal_phy_write()
276 		return -EOPNOTSUPP;  in lan937x_internal_phy_write()
297 		dev_err(dev->dev, "Failed to write phy register\n");  in lan937x_internal_phy_write()
310 	/* Check for internal phy port, return 0xffff for non-existent phy */  in lan937x_internal_phy_read()
311 	if (!dev->info->internal_phy[addr])  in lan937x_internal_phy_read()
327 		dev_err(dev->dev, "Failed to read phy register\n");  in lan937x_internal_phy_read()
378 	const u32 *masks = dev->info->masks;  in lan937x_port_setup()
379 	const u16 *regs = dev->info->regs;  in lan937x_port_setup()
380 	struct dsa_switch *ds = dev->ds;  in lan937x_port_setup()
398 	if (!dev->info->internal_phy[port])  in lan937x_port_setup()
409 	dev->dev_ops->cfg_port_member(dev, port, member);  in lan937x_port_setup()
414 	struct ksz_device *dev = ds->priv;  in lan937x_config_cpu_port()
418 		if (dev->info->cpu_ports & (1 << dp->index)) {  in lan937x_config_cpu_port()
419 			dev->cpu_port = dp->index;  in lan937x_config_cpu_port()
422 			lan937x_port_setup(dev, dp->index, true);  in lan937x_config_cpu_port()
427 		ksz_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED);  in lan937x_config_cpu_port()
433 	struct dsa_switch *ds = dev->ds;  in lan937x_change_mtu()
448 		dev_err(ds->dev, "failed to enable jumbo\n");  in lan937x_change_mtu()
455 		dev_err(ds->dev, "failed to update mtu for port %d\n", port);  in lan937x_change_mtu()
470 #define MAX_TIMER_VAL	((1 << 20) - 1)  in lan937x_set_ageing_time()
472 	/* The aging timer comprises a 3-bit multiplier and a 20-bit second  in lan937x_set_ageing_time()
488 		return -EINVAL;  in lan937x_set_ageing_time()
546 	/* write DLL reset to take effect */  in lan937x_set_tune_adj()
575 			      struct phylink_config *config)  in lan937x_phylink_get_caps()  argument
577 	config->mac_capabilities = MAC_100FD;  in lan937x_phylink_get_caps()
579 	if (dev->info->supports_rgmii[port]) {  in lan937x_phylink_get_caps()
581 		config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE |  in lan937x_phylink_get_caps()
584 		config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE |  in lan937x_phylink_get_caps()
591 	struct ksz_port *p = &dev->ports[port];  in lan937x_setup_rgmii_delay()
593 	if (p->rgmii_tx_val) {  in lan937x_setup_rgmii_delay()
595 		dev_info(dev->dev, "Applied rgmii tx delay for the port %d\n",  in lan937x_setup_rgmii_delay()
599 	if (p->rgmii_rx_val) {  in lan937x_setup_rgmii_delay()
601 		dev_info(dev->dev, "Applied rgmii rx delay for the port %d\n",  in lan937x_setup_rgmii_delay()
613 	dev->port_mask = (1 << dev->info->port_cnt) - 1;  in lan937x_switch_init()
620 	struct ksz_device *dev = ds->priv;  in lan937x_setup()
626 	ds->vlan_filtering_is_global = true;  in lan937x_setup()