| /linux/drivers/gpu/drm/radeon/ |
| H A D | rv740_dpm.c | 123 struct atom_clock_dividers dividers; in rv740_populate_sclk_value() local
136 engine_clock, false, ÷rs); in rv740_populate_sclk_value()
140 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()
142 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
147 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv740_populate_sclk_value()
148 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value()
159 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
198 struct atom_clock_dividers dividers; in rv740_populate_mclk_value() local
204 memory_clock, false, ÷rs); in rv740_populate_mclk_value()
208 ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in rv740_populate_mclk_value()
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| H A D | rv730_dpm.c | 42 struct atom_clock_dividers dividers; in rv730_populate_sclk_value() local
55 engine_clock, false, ÷rs); in rv730_populate_sclk_value()
59 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()
61 if (dividers.enable_post_div) in rv730_populate_sclk_value()
62 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
63 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
72 if (dividers.enable_post_div) in rv730_populate_sclk_value()
77 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv730_populate_sclk_value()
78 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value()
79 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_sclk_value()
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| H A D | rv6xx_dpm.c | 142 struct atom_clock_dividers dividers; in rv6xx_convert_clock_to_stepping() local
145 clock, false, ÷rs); in rv6xx_convert_clock_to_stepping()
149 if (dividers.enable_post_div) in rv6xx_convert_clock_to_stepping()
150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
526 struct atom_clock_dividers *dividers, in rv6xx_calculate_vco_frequency() argument
529 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / in rv6xx_calculate_vco_frequency()
530 (dividers->ref_div + 1); in rv6xx_calculate_vco_frequency()
553 struct atom_clock_dividers dividers; in rv6xx_program_engine_spread_spectrum() local
560 …if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, ÷rs) == 0) { in rv6xx_program_engine_spread_spectrum()
561 vco_freq = rv6xx_calculate_vco_frequency(ref_clk, ÷rs, in rv6xx_program_engine_spread_spectrum()
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| H A D | rv770_dpm.c | 322 struct atom_clock_dividers *dividers, in rv770_calculate_fractional_mpll_feedback_divider() argument
334 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
335 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()
404 struct atom_clock_dividers dividers; in rv770_populate_mclk_value() local
412 memory_clock, false, ÷rs); in rv770_populate_mclk_value()
416 if ((dividers.ref_div < 1) || (dividers.ref_div > 5)) in rv770_populate_mclk_value()
421 ÷rs, &clkf, &clkfrac); in rv770_populate_mclk_value()
423 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); in rv770_populate_mclk_value()
434 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); in rv770_populate_mclk_value()
440 if (dividers.vco_mode) in rv770_populate_mclk_value()
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| H A D | cypress_dpm.c | 493 struct atom_clock_dividers dividers; in cypress_populate_mclk_value() local
500 memory_clock, strobe_mode, ÷rs); in cypress_populate_mclk_value()
508 dividers.post_div = 1; in cypress_populate_mclk_value()
511 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in cypress_populate_mclk_value()
518 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
519 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in cypress_populate_mclk_value()
520 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div); in cypress_populate_mclk_value()
521 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div); in cypress_populate_mclk_value()
524 if (dividers.vco_mode) in cypress_populate_mclk_value()
535 mpll_dq_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
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| H A D | rs780_dpm.c | 78 struct atom_clock_dividers dividers; in rs780_initialize_dpm_power_state() local
83 default_state->sclk_low, false, ÷rs); in rs780_initialize_dpm_power_state()
87 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); in rs780_initialize_dpm_power_state()
88 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); in rs780_initialize_dpm_power_state()
89 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state()
91 if (dividers.enable_post_div) in rs780_initialize_dpm_power_state()
1032 struct atom_clock_dividers dividers; in rs780_dpm_force_performance_level() local
1043 ps->sclk_high, false, ÷rs); in rs780_dpm_force_performance_level()
1047 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
1050 ps->sclk_low, false, ÷rs); in rs780_dpm_force_performance_level()
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| /linux/sound/soc/codecs/ |
| H A D | wm8510.h | 61 /* DAC clock dividers */
65 /* ADC clock dividers */
69 /* PLL Out dividers */
75 /* BCLK clock dividers */
83 /* MCLK clock dividers */
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| H A D | wm8940.h | 74 /* MCLK clock dividers */
84 /* BCLK clock dividers */
92 /* PLL Out Dividers */
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| H A D | wm8974.h | 59 /* PLL Out dividers */
65 /* BCLK clock dividers */
73 /* MCLK clock dividers */
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| H A D | wm8753.h | 87 /* PCM clock dividers */
96 /* BCLK clock dividers */
103 /* VXCLK clock dividers */
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| /linux/Documentation/devicetree/bindings/hwmon/ |
| H A D | adi,ltc4282.yaml | 51 adi,overvoltage-dividers:
53 Select which dividers to use for VDD Overvoltage detection. Note that
54 when the internal dividers are used the threshold is referenced to VDD.
63 adi,undervoltage-dividers:
65 Select which dividers to use for VDD Overvoltage detection. Note that
66 when the internal dividers are used the threshold is referenced to VDD.
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| /linux/drivers/gpu/drm/renesas/rcar-du/ |
| H A D | rcar_dw_hdmi.c | 17 #define RCAR_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL dividers */
19 #define RCAR_HDMI_PHY_PLLDIVCTRL 0x11 /* PLL dividers */
23 u16 opmode_div; /* Mode of operation and PLL dividers */
25 u16 div; /* PLL dividers */
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| /linux/drivers/clk/samsung/ |
| H A D | clk-cpu.c | 160 * Helper function to set the 'safe' dividers for the CPU clock. The parameters
162 * dividers to be programmed.
218 * the values for DIV_COPY and DIV_HPM dividers need not be set. in exynos_cpuclk_pre_rate_change()
231 * the armclk speed is more than the old_prate until the dividers are in exynos_cpuclk_pre_rate_change()
232 * set. Also workaround the issue of the dividers being set to lower in exynos_cpuclk_pre_rate_change()
260 /* alternate parent is active now. set the dividers */ in exynos_cpuclk_pre_rate_change()
352 * the armclk speed is more than the old_prate until the dividers are in exynos5433_cpuclk_pre_rate_change()
353 * set. Also workaround the issue of the dividers being set to lower in exynos5433_cpuclk_pre_rate_change()
373 /* alternate parent is active now. set the dividers */ in exynos5433_cpuclk_pre_rate_change()
504 * the armclk speed is more than the old_prate until the dividers are in exynos850_cpuclk_pre_rate_change()
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-cpu.c | 48 * @rate_table: pll-rates and their associated dividers
103 /* alternate parent is active now. set the dividers */ in rockchip_cpuclk_set_dividers()
176 * the armclk speed is more than the old_rate until the dividers are in rockchip_cpuclk_pre_rate_change()
180 /* calculate dividers */ in rockchip_cpuclk_pre_rate_change()
189 * Change parents and add dividers in a single transaction. in rockchip_cpuclk_pre_rate_change()
192 * dividing the primary parent by the extra dividers that were in rockchip_cpuclk_pre_rate_change()
244 * post-rate change event, re-mux to primary parent and remove dividers. in rockchip_cpuclk_post_rate_change()
247 * primary parent by the extra dividers that were needed for the alt. in rockchip_cpuclk_post_rate_change()
263 /* remove dividers */ in rockchip_cpuclk_post_rate_change()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | polaris10_smumgr.c | 895 struct pp_atomctrl_clock_dividers_ai dividers; in polaris10_calculate_sclk_params() local
903 /* get the engine clock dividers for this clock value */ in polaris10_calculate_sclk_params()
904 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); in polaris10_calculate_sclk_params()
906 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in polaris10_calculate_sclk_params()
907 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in polaris10_calculate_sclk_params()
908 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in polaris10_calculate_sclk_params()
909 sclk_setting->PllRange = dividers.ucSclkPllRange; in polaris10_calculate_sclk_params()
911 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in polaris10_calculate_sclk_params()
913 sclk_setting->SSc_En = dividers.ucSscEnable; in polaris10_calculate_sclk_params()
914 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; in polaris10_calculate_sclk_params()
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| H A D | vegam_smumgr.c | 724 struct pp_atomctrl_clock_dividers_ai dividers; in vegam_calculate_sclk_params() local
732 /* get the engine clock dividers for this clock value */ in vegam_calculate_sclk_params()
733 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); in vegam_calculate_sclk_params()
735 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in vegam_calculate_sclk_params()
736 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in vegam_calculate_sclk_params()
737 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in vegam_calculate_sclk_params()
738 sclk_setting->PllRange = dividers.ucSclkPllRange; in vegam_calculate_sclk_params()
740 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in vegam_calculate_sclk_params()
742 sclk_setting->SSc_En = dividers.ucSscEnable; in vegam_calculate_sclk_params()
743 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; in vegam_calculate_sclk_params()
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| H A D | fiji_smumgr.c | 859 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_calculate_sclk_params() local
870 /* get the engine clock dividers for this clock value */ in fiji_calculate_sclk_params()
871 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs); in fiji_calculate_sclk_params()
874 "Error retrieving Engine Clock dividers from VBIOS.", in fiji_calculate_sclk_params()
879 ref_divider = 1 + dividers.uc_pll_ref_div; in fiji_calculate_sclk_params()
882 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in fiji_calculate_sclk_params()
886 SPLL_REF_DIV, dividers.uc_pll_ref_div); in fiji_calculate_sclk_params()
888 SPLL_PDIV_A, dividers.uc_pll_post_div); in fiji_calculate_sclk_params()
902 uint32_t vco_freq = clock * dividers.uc_pll_post_div; in fiji_calculate_sclk_params()
931 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in fiji_calculate_sclk_params()
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| H A D | ci_smumgr.c | 301 struct pp_atomctrl_clock_dividers_vi dividers; in ci_calculate_sclk_params() local
312 /* get the engine clock dividers for this clock value */ in ci_calculate_sclk_params()
313 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs); in ci_calculate_sclk_params()
316 "Error retrieving Engine Clock dividers from VBIOS.", in ci_calculate_sclk_params()
321 ref_divider = 1 + dividers.uc_pll_ref_div; in ci_calculate_sclk_params()
324 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in ci_calculate_sclk_params()
328 SPLL_REF_DIV, dividers.uc_pll_ref_div); in ci_calculate_sclk_params()
330 SPLL_PDIV_A, dividers.uc_pll_post_div); in ci_calculate_sclk_params()
343 uint32_t vco_freq = clock * dividers.uc_pll_post_div; in ci_calculate_sclk_params()
366 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in ci_calculate_sclk_params()
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| /linux/sound/soc/pxa/ |
| H A D | pxa-ssp.h | 16 /* SSP audio dividers */
21 /* SSP ACDS audio dividers values */
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| /linux/drivers/ssb/ |
| H A D | main.c | 858 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ in ssb_calc_clock_rate()
859 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ in ssb_calc_clock_rate()
860 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ in ssb_calc_clock_rate()
861 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ in ssb_calc_clock_rate()
865 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */ in ssb_calc_clock_rate()
871 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */ in ssb_calc_clock_rate()
878 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ in ssb_calc_clock_rate()
879 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ in ssb_calc_clock_rate()
894 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ in ssb_calc_clock_rate()
895 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ in ssb_calc_clock_rate()
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | mediatek,mt8188-sys-clock.yaml | 15 dividers -->
21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
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| H A D | mediatek,mt8186-sys-clock.yaml | 15 dividers -->
21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
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| H A D | mediatek,mt8195-sys-clock.yaml | 15 dividers -->
21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
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| /linux/arch/mips/alchemy/common/ |
| H A D | clock.c | 11 * Dividers:
12 * - 6 clock dividers with:
19 * * take either AUXPLL or one of the above 6 dividers as input,
53 * the internal sources which can be driven by the PLLs and dividers.
366 /* Clock dividers and muxes *******************************************/
368 /* data for fgen and csrc mux-dividers */
670 * dividers behave exactly as on previous models (dividers are multiples
671 * of 2); with the bit set, dividers are multiples of 1, halving their
1093 /* Frequency dividers 0-5 */ in alchemy_clk_init()
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| /linux/include/linux/mfd/wm8350/ |
| H A D | audio.h | 530 /* ADC clock dividers */
539 /* ADC clock dividers */
548 /* BCLK clock dividers */
566 /* Sys (MCLK) clock dividers */
570 /* OP clock dividers */
|