Lines Matching full:dividers

858 	case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */  in ssb_calc_clock_rate()
859 	case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */  in ssb_calc_clock_rate()
860 	case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */  in ssb_calc_clock_rate()
861 	case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */  in ssb_calc_clock_rate()
865 	case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */  in ssb_calc_clock_rate()
871 	case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */  in ssb_calc_clock_rate()
878 	case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */  in ssb_calc_clock_rate()
879 	case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */  in ssb_calc_clock_rate()
894 	case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */  in ssb_calc_clock_rate()
895 	case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */  in ssb_calc_clock_rate()
896 	case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */  in ssb_calc_clock_rate()
897 	case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */  in ssb_calc_clock_rate()
963 		if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */  in ssb_clockspeed()