xref: /linux/sound/soc/codecs/wm8974.h (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
20a1bf553SMark Brown /*
30a1bf553SMark Brown  * wm8974.h  --  WM8974 Soc Audio driver
40a1bf553SMark Brown  */
50a1bf553SMark Brown 
60a1bf553SMark Brown #ifndef _WM8974_H
70a1bf553SMark Brown #define _WM8974_H
80a1bf553SMark Brown 
90a1bf553SMark Brown /* WM8974 register space */
100a1bf553SMark Brown 
110a1bf553SMark Brown #define WM8974_RESET		0x0
120a1bf553SMark Brown #define WM8974_POWER1		0x1
130a1bf553SMark Brown #define WM8974_POWER2		0x2
140a1bf553SMark Brown #define WM8974_POWER3		0x3
150a1bf553SMark Brown #define WM8974_IFACE		0x4
160a1bf553SMark Brown #define WM8974_COMP		0x5
170a1bf553SMark Brown #define WM8974_CLOCK		0x6
180a1bf553SMark Brown #define WM8974_ADD		0x7
190a1bf553SMark Brown #define WM8974_GPIO		0x8
200a1bf553SMark Brown #define WM8974_DAC		0xa
210a1bf553SMark Brown #define WM8974_DACVOL		0xb
220a1bf553SMark Brown #define WM8974_ADC		0xe
230a1bf553SMark Brown #define WM8974_ADCVOL		0xf
240a1bf553SMark Brown #define WM8974_EQ1		0x12
250a1bf553SMark Brown #define WM8974_EQ2		0x13
260a1bf553SMark Brown #define WM8974_EQ3		0x14
270a1bf553SMark Brown #define WM8974_EQ4		0x15
280a1bf553SMark Brown #define WM8974_EQ5		0x16
290a1bf553SMark Brown #define WM8974_DACLIM1		0x18
300a1bf553SMark Brown #define WM8974_DACLIM2		0x19
310a1bf553SMark Brown #define WM8974_NOTCH1		0x1b
320a1bf553SMark Brown #define WM8974_NOTCH2		0x1c
330a1bf553SMark Brown #define WM8974_NOTCH3		0x1d
340a1bf553SMark Brown #define WM8974_NOTCH4		0x1e
350a1bf553SMark Brown #define WM8974_ALC1		0x20
360a1bf553SMark Brown #define WM8974_ALC2		0x21
370a1bf553SMark Brown #define WM8974_ALC3		0x22
380a1bf553SMark Brown #define WM8974_NGATE		0x23
390a1bf553SMark Brown #define WM8974_PLLN		0x24
400a1bf553SMark Brown #define WM8974_PLLK1		0x25
410a1bf553SMark Brown #define WM8974_PLLK2		0x26
420a1bf553SMark Brown #define WM8974_PLLK3		0x27
430a1bf553SMark Brown #define WM8974_ATTEN		0x28
440a1bf553SMark Brown #define WM8974_INPUT		0x2c
450a1bf553SMark Brown #define WM8974_INPPGA		0x2d
460a1bf553SMark Brown #define WM8974_ADCBOOST		0x2f
470a1bf553SMark Brown #define WM8974_OUTPUT		0x31
480a1bf553SMark Brown #define WM8974_SPKMIX		0x32
490a1bf553SMark Brown #define WM8974_SPKVOL		0x36
500a1bf553SMark Brown #define WM8974_MONOMIX		0x38
510a1bf553SMark Brown 
520a1bf553SMark Brown #define WM8974_CACHEREGNUM 	57
530a1bf553SMark Brown 
540a1bf553SMark Brown /* Clock divider Id's */
550a1bf553SMark Brown #define WM8974_OPCLKDIV		0
560a1bf553SMark Brown #define WM8974_MCLKDIV		1
57b2c3e923SGuennadi Liakhovetski #define WM8974_BCLKDIV		2
580a1bf553SMark Brown 
590a1bf553SMark Brown /* PLL Out dividers */
600a1bf553SMark Brown #define WM8974_OPCLKDIV_1	(0 << 4)
610a1bf553SMark Brown #define WM8974_OPCLKDIV_2	(1 << 4)
620a1bf553SMark Brown #define WM8974_OPCLKDIV_3	(2 << 4)
630a1bf553SMark Brown #define WM8974_OPCLKDIV_4	(3 << 4)
640a1bf553SMark Brown 
650a1bf553SMark Brown /* BCLK clock dividers */
660a1bf553SMark Brown #define WM8974_BCLKDIV_1	(0 << 2)
670a1bf553SMark Brown #define WM8974_BCLKDIV_2	(1 << 2)
680a1bf553SMark Brown #define WM8974_BCLKDIV_4	(2 << 2)
690a1bf553SMark Brown #define WM8974_BCLKDIV_8	(3 << 2)
700a1bf553SMark Brown #define WM8974_BCLKDIV_16	(4 << 2)
710a1bf553SMark Brown #define WM8974_BCLKDIV_32	(5 << 2)
720a1bf553SMark Brown 
730a1bf553SMark Brown /* MCLK clock dividers */
740a1bf553SMark Brown #define WM8974_MCLKDIV_1	(0 << 5)
750a1bf553SMark Brown #define WM8974_MCLKDIV_1_5	(1 << 5)
760a1bf553SMark Brown #define WM8974_MCLKDIV_2	(2 << 5)
770a1bf553SMark Brown #define WM8974_MCLKDIV_3	(3 << 5)
780a1bf553SMark Brown #define WM8974_MCLKDIV_4	(4 << 5)
790a1bf553SMark Brown #define WM8974_MCLKDIV_6	(5 << 5)
800a1bf553SMark Brown #define WM8974_MCLKDIV_8	(6 << 5)
810a1bf553SMark Brown #define WM8974_MCLKDIV_12	(7 << 5)
820a1bf553SMark Brown 
830a1bf553SMark Brown #endif
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