| /linux/drivers/clk/ti/ |
| H A D | divider.c | 3 * TI Divider Clock
32 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument
38 if (divider->table) { in _setup_mask()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
45 max_val = divider->max; in _setup_mask()
47 if (!(divider->flags & CLK_DIVIDER_ONE_BASED) && in _setup_mask()
48 !(divider->flags & CLK_DIVIDER_POWER_OF_TWO)) in _setup_mask()
52 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in _setup_mask()
57 divider->mask = (1 << fls(mask)) - 1; in _setup_mask()
60 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val) in _get_div() argument
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| H A D | clk-dra7-atl.c | 49 u32 divider; /* Cached divider value */ member
85 cdesc->divider - 1); in atl_clk_enable()
120 return parent_rate / cdesc->divider; in atl_clk_recalc_rate()
126 unsigned divider; in atl_clk_determine_rate() local
128 divider = (req->best_parent_rate + req->rate / 2) / req->rate; in atl_clk_determine_rate()
129 if (divider > DRA7_ATL_DIVIDER_MASK + 1) in atl_clk_determine_rate()
130 divider = DRA7_ATL_DIVIDER_MASK + 1; in atl_clk_determine_rate()
132 req->rate = req->best_parent_rate / divider; in atl_clk_determine_rate()
141 u32 divider; in atl_clk_set_rate() local
147 divider = ((parent_rate + rate / 2) / rate) - 1; in atl_clk_set_rate()
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| /linux/drivers/clk/tegra/ |
| H A D | clk-divider.c | 21 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, in get_div() argument
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
38 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_recalc_rate() local
43 reg = readl_relaxed(divider->reg); in clk_frac_div_recalc_rate()
45 if ((divider->flags & TEGRA_DIVIDER_UART) && in clk_frac_div_recalc_rate()
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
51 mul = get_mul(divider); in clk_frac_div_recalc_rate()
64 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_determine_rate() local
74 div = get_div(divider, req->rate, output_rate); in clk_frac_div_determine_rate()
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| H A D | clk.h | 95 * struct tegra_clk_frac_div - fractional divider clock
98 * @reg: register containing divider
100 * @shift: shift to the divider bit field
101 * @width: width of the divider bit field
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
108 * flag indicates that this divider is for fixed rate PLL.
110 * fraction bit is set. This flags indicates to calculate divider for which
112 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
113 * set when divider value is not 0. This flags indicates that the divider
158 * @n: feedback divider
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| /linux/drivers/clk/baikal-t1/ |
| H A D | ccu-div.h | 17 * CCU Divider private clock IDs
25 * CCU Divider private flags
26 * @CCU_DIV_BASIC: Basic divider clock required by the kernel as early as
28 * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
30 * @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3].
42 * enum ccu_div_type - CCU Divider types
43 * @CCU_DIV_VAR: Clocks gate with variable divider.
44 * @CCU_DIV_GATE: Clocks gate with fixed divider.
45 * @CCU_DIV_BUF: Clock gate with no divider.
46 * @CCU_DIV_FIXED: Ungateable clock with fixed divider.
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| H A D | ccu-div.c | 78 unsigned long divider) in ccu_div_var_update_clkdiv() argument
85 nd = ccu_div_lock_delay_ns(parent_rate, divider); in ccu_div_var_update_clkdiv()
135 pr_err("Divider '%s' lock timed out\n", clk_hw_get_name(hw)); in ccu_div_var_enable()
211 unsigned long divider; in ccu_div_var_recalc_rate() local
215 divider = ccu_div_get(div->mask, val); in ccu_div_var_recalc_rate()
217 return ccu_div_calc_freq(parent_rate, divider); in ccu_div_var_recalc_rate()
224 unsigned long divider; in ccu_div_var_calc_divider() local
226 divider = parent_rate / rate; in ccu_div_var_calc_divider()
227 return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN, in ccu_div_var_calc_divider()
235 unsigned long divider; in ccu_div_var_determine_rate() local
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| /linux/drivers/clk/xilinx/ |
| H A D | clk-xlnx-clock-wizard.c | 88 /* Divider limits, from UG572 Table 3-4 for Ultrascale+ */
114 /* Extract divider instance from clock hardware instance */
148 * struct clk_wzrd_divider - clock divider specific to clk_wzrd
151 * @base: base address of register containing the divider
152 * @offset: offset address of register containing the divider
153 * @shift: shift to the divider bit field
154 * @width: width of the divider bit field
155 * @flags: clk_wzrd divider flags
156 * @table: array of value/divider pairs, last entry should have div = 0
159 * @d: value of the common divider
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| /linux/drivers/clk/mvebu/ |
| H A D | dove-divider.c | 3 * Marvell Dove PMU Core PLL divider driver
15 #include "dove-divider.h"
53 unsigned int divider; in dove_get_divider() local
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
64 return divider; in dove_get_divider()
70 unsigned int divider, max; in dove_calc_divider() local
72 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in dove_calc_divider()
78 if (divider == dc->divider_table[i]) { in dove_calc_divider()
79 divider = i; in dove_calc_divider()
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| /linux/include/dt-bindings/clock/ |
| H A D | tegra234-clock.h | 36 /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
52 * divided by the divider controlled by ACLK_CLK_DIVISOR in
56 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */
60 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */
62 /** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */
64 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */
81 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */
83 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */
87 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider gated output */
152 /** @brief CLK_RST_CONTROLLER_MAUDCLK_OUT_SWITCH_DIVIDER switch divider output (maudclk) */
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| /linux/drivers/clk/zynqmp/ |
| H A D | divider.c | 3 * Zynq UltraScale+ MPSoC Divider support
7 * Adjustable divider clock implementation
16 * DOC: basic adjustable divider clock that cannot gate
32 * struct zynqmp_clk_divider - adjustable divider clock
35 * @is_frac: The divider is a fractional divider
73 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
82 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_recalc_rate() local
84 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate()
85 u32 div_type = divider->div_type; in zynqmp_clk_divider_recalc_rate()
92 pr_debug("%s() get divider failed for %s, ret = %d\n", in zynqmp_clk_divider_recalc_rate()
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| /linux/drivers/clk/ |
| H A D | clk-divider.c | 7 * Adjustable divider clock implementation
20 * DOC: basic adjustable divider clock that cannot gate
29 static inline u32 clk_div_readl(struct clk_divider *divider) in clk_div_readl() argument
31 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_readl()
32 return ioread32be(divider->reg); in clk_div_readl()
34 return readl(divider->reg); in clk_div_readl()
37 static inline void clk_div_writel(struct clk_divider *divider, u32 val) in clk_div_writel() argument
39 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_writel()
40 iowrite32be(val, divider->reg); in clk_div_writel()
42 writel(val, divider->reg); in clk_div_writel()
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| H A D | clk-milbeaut.c | 379 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_recalc_rate() local
382 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_recalc_rate()
383 val &= clk_div_mask(divider->width); in m10v_clk_divider_recalc_rate()
385 return divider_recalc_rate(hw, parent_rate, val, divider->table, in m10v_clk_divider_recalc_rate()
386 divider->flags, divider->width); in m10v_clk_divider_recalc_rate()
392 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_determine_rate() local
395 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in m10v_clk_divider_determine_rate()
398 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_determine_rate()
399 val &= clk_div_mask(divider->width); in m10v_clk_divider_determine_rate()
401 return divider_ro_determine_rate(hw, req, divider->table, in m10v_clk_divider_determine_rate()
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-half-divider.c | 25 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_recalc_rate() local
28 val = readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate()
29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
60 * The maximum divider we can use without overflowing in clk_half_divider_bestdiv()
70 * parent rate, so return the divider immediately. in clk_half_divider_bestdiv()
98 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_determine_rate() local
102 divider->width, in clk_half_divider_determine_rate()
103 divider->flags); in clk_half_divider_determine_rate()
113 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_set_rate() local
120 value = min_t(unsigned int, value, div_mask(divider->width)); in clk_half_divider_set_rate()
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| /linux/drivers/clk/imx/ |
| H A D | clk-fixup-div.c | 15 * struct clk_fixup_div - imx integer fixup divider clock
16 * @divider: the parent class
20 * The imx fixup divider clock is a subclass of basic clk_divider
24 struct clk_divider divider; member
31 struct clk_divider *divider = to_clk_divider(hw); in to_clk_fixup_div() local
33 return container_of(divider, struct clk_fixup_div, divider); in to_clk_fixup_div()
41 return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate); in clk_fixup_div_recalc_rate()
49 return fixup_div->ops->determine_rate(&fixup_div->divider.hw, req); in clk_fixup_div_determine_rate()
57 unsigned int divider, value; in clk_fixup_div_set_rate() local
61 divider = parent_rate / rate; in clk_fixup_div_set_rate()
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| H A D | clk-composite-8m.c | 31 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_recalc_rate() local
36 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
40 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
41 divider->width); in imx8m_clk_composite_divider_recalc_rate()
43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
47 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
80 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_set_rate() local
92 spin_lock_irqsave(divider->lock, flags); in imx8m_clk_composite_divider_set_rate()
94 orig = readl(divider->reg); in imx8m_clk_composite_divider_set_rate()
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| H A D | clk-composite-93.c | 110 struct clk_divider *divider = to_clk_divider(hw); in imx93_clk_composite_divider_set_rate() local
116 value = divider_get_val(rate, parent_rate, divider->table, divider->width, divider->flags); in imx93_clk_composite_divider_set_rate()
120 if (divider->lock) in imx93_clk_composite_divider_set_rate()
121 spin_lock_irqsave(divider->lock, flags); in imx93_clk_composite_divider_set_rate()
123 val = readl(divider->reg); in imx93_clk_composite_divider_set_rate()
124 val &= ~(clk_div_mask(divider->width) << divider->shift); in imx93_clk_composite_divider_set_rate()
125 val |= (u32)value << divider->shift; in imx93_clk_composite_divider_set_rate()
126 writel(val, divider->reg); in imx93_clk_composite_divider_set_rate()
128 ret = imx93_clk_composite_wait_ready(hw, divider->reg); in imx93_clk_composite_divider_set_rate()
130 if (divider->lock) in imx93_clk_composite_divider_set_rate()
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| H A D | clk-divider-gate.c | 15 struct clk_divider divider; member
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
170 * NOTE: In order to reuse the most code from the common divider,
171 * we also design our divider following the way that provids an extra
201 div_gate->divider.reg = reg; in imx_clk_hw_divider_gate()
202 div_gate->divider.shift = shift; in imx_clk_hw_divider_gate()
203 div_gate->divider.width = width; in imx_clk_hw_divider_gate()
204 div_gate->divider.lock = lock; in imx_clk_hw_divider_gate()
205 div_gate->divider.table = table; in imx_clk_hw_divider_gate()
206 div_gate->divider.hw.init = &init; in imx_clk_hw_divider_gate()
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| /linux/drivers/clk/mxs/ |
| H A D | clk-div.c | 12 * struct clk_div - mxs integer divider clock
13 * @divider: the parent class
18 * The mxs divider clock is a subclass of basic clk_divider with an
22 struct clk_divider divider; member
30 struct clk_divider *divider = to_clk_divider(hw); in to_clk_div() local
32 return container_of(divider, struct clk_div, divider); in to_clk_div()
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
48 return div->ops->determine_rate(&div->divider.hw, req); in clk_div_determine_rate()
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
90 div->divider.reg = reg; in mxs_clk_div()
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| /linux/drivers/media/tuners/ |
| H A D | tda18218_priv.h | 20 #define R07_MD1 0x07 /* Main divider byte 1 */
22 #define R09_MD2 0x09 /* Main divider byte 2 */
23 #define R0A_MD3 0x0a /* Main divider byte 1 */
24 #define R0B_MD4 0x0b /* Main divider byte 4 */
25 #define R0C_MD5 0x0c /* Main divider byte 5 */
26 #define R0D_MD6 0x0d /* Main divider byte 6 */
27 #define R0E_MD7 0x0e /* Main divider byte 7 */
28 #define R0F_MD8 0x0f /* Main divider byte 8 */
29 #define R10_CD1 0x10 /* Call divider byte 1 */
30 #define R11_CD2 0x11 /* Call divider byte 2 */
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_pll.c | 70 * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
75 * @post_div: post divider
76 * @fb_div_max: feedback divider maximum
77 * @ref_div_max: reference divider maximum
78 * @fb_div: resulting feedback divider
79 * @ref_div: resulting reference divider
81 * Calculate feedback and reference divider for a given post divider. Makes
90 /* limit reference * post divider to a maximum */ in amdgpu_pll_get_fb_ref_div()
96 /* get matching reference and feedback divider */ in amdgpu_pll_get_fb_ref_div()
100 /* limit fb divider to its maximum */ in amdgpu_pll_get_fb_ref_div()
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| /linux/drivers/clk/bcm/ |
| H A D | clk-kona.h | 220 * output rate of the clock. Each divider can be either fixed or
221 * variable. If there are two dividers, they are the "pre-divider"
222 * and the "regular" or "downstream" divider. If there is only one,
223 * there is no pre-divider.
225 * A fixed divider is any non-zero (positive) value, and it
226 * indicates how the input rate is affected by the divider.
228 * The value of a variable divider is maintained in a sub-field of a
229 * 32-bit divider register. The position of the field in the
233 * In addition, a variable divider can indicate that some subset
234 * of its bits represent a "fractional" part of the divider. Such
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| H A D | clk-kona.c | 48 /* Divider and scaling helpers */
50 /* Convert a divider into the scaled divisor value it represents. */
56 /* The scaled minimum divisor representable by a divider */
66 /* The scaled maximum divisor representable by a divider */
80 * Convert a scaled divisor into its divider representation as
81 * stored in a divider register field.
84 divider(struct bcm_clk_div *div, u64 scaled_div) in divider() function
536 /* Divider operations */
538 /* Read a divider value and return the scaled divisor it represents. */
552 /* Extract the full divider field from the register value */ in divider_read_scaled()
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| /linux/drivers/clk/davinci/ |
| H A D | pll.c | 229 * @fixed: if true, the divider is a fixed value
242 struct clk_divider *divider; in davinci_pll_div_register() local
253 divider = kzalloc_obj(*divider); in davinci_pll_div_register()
254 if (!divider) { in davinci_pll_div_register()
259 divider->reg = reg; in davinci_pll_div_register()
260 divider->shift = DIV_RATIO_SHIFT; in davinci_pll_div_register()
261 divider->width = DIV_RATIO_WIDTH; in davinci_pll_div_register()
264 divider->flags |= CLK_DIVIDER_READ_ONLY; in davinci_pll_div_register()
269 NULL, NULL, ÷r->hw, divider_ops, in davinci_pll_div_register()
279 kfree(divider); in davinci_pll_div_register()
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | keystone-pll.txt | 2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
27 reg-names = "control", "multiplier", "post-divider";
64 - compatible : shall be "ti,keystone,pll-divider-clock"
68 - bit-mask : arbitrary bitmask for programming the divider
76 compatible = "ti,keystone,pll-divider-clock";
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| /linux/sound/soc/ti/ |
| H A D | omap-dmic.c | 125 int divider = -EINVAL; in omap_dmic_select_divider() local
133 divider = 0x6; /* Divider: 5 (192KHz sampling rate) */ in omap_dmic_select_divider()
138 return divider; in omap_dmic_select_divider()
145 divider = 0x4; /* Divider: 16 */ in omap_dmic_select_divider()
150 divider = 0x5; /* Divider: 5 */ in omap_dmic_select_divider()
153 divider = 0x0; /* Divider: 8 */ in omap_dmic_select_divider()
156 divider = 0x2; /* Divider: 10 */ in omap_dmic_select_divider()
165 divider = 0x3; /* Divider: 8 */ in omap_dmic_select_divider()
170 divider = 0x1; /* Divider: 5 (96KHz sampling rate) */ in omap_dmic_select_divider()
178 return divider; in omap_dmic_select_divider()
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