88 /* Divider limits, from UG572 Table 3-4 for Ultrascale+ */
114 /* Extract divider instance from clock hardware instance */
148  * struct clk_wzrd_divider - clock divider specific to clk_wzrd
151  * @base:	base address of register containing the divider
152  * @offset:	offset address of register containing the divider
153  * @shift:	shift to the divider bit field
154  * @width:	width of the divider bit field
155  * @flags:	clk_wzrd divider flags
156  * @table:	array of value/divider pairs, last entry should have div = 0
159  * @d:	value of the common divider
160  * @o:	value of the leaf divider
161  * @o_frac:	value of the fractional leaf divider
177 	spinlock_t *lock;  /* divider lock */
199 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_rate_ver()  local
200 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_recalc_rate_ver()
224 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_rate()  local
225 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_recalc_rate()
228 	val = readl(div_addr) >> divider->shift;  in clk_wzrd_recalc_rate()
229 	val &= div_mask(divider->width);  in clk_wzrd_recalc_rate()
231 	return divider_recalc_rate(hw, parent_rate, val, divider->table,  in clk_wzrd_recalc_rate()
232 			divider->flags, divider->width);  in clk_wzrd_recalc_rate()
238 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_ver_dynamic_reconfig()  local
239 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_ver_dynamic_reconfig()
244 	spin_lock_irqsave(divider->lock, flags);  in clk_wzrd_ver_dynamic_reconfig()
264 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,  in clk_wzrd_ver_dynamic_reconfig()
272 	       divider->base + WZRD_DR_INIT_VERSAL_OFFSET);  in clk_wzrd_ver_dynamic_reconfig()
275 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,  in clk_wzrd_ver_dynamic_reconfig()
279 	spin_unlock_irqrestore(divider->lock, flags);  in clk_wzrd_ver_dynamic_reconfig()
286 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_reconfig()  local
287 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_dynamic_reconfig()
292 	spin_lock_irqsave(divider->lock, flags);  in clk_wzrd_dynamic_reconfig()
304 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,  in clk_wzrd_dynamic_reconfig()
312 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig()
314 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig()
317 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,  in clk_wzrd_dynamic_reconfig()
321 	spin_unlock_irqrestore(divider->lock, flags);  in clk_wzrd_dynamic_reconfig()
344 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_get_divisors_ver()  local
372 				divider->m = m;  in clk_wzrd_get_divisors_ver()
373 				divider->d = d;  in clk_wzrd_get_divisors_ver()
374 				divider->o = o;  in clk_wzrd_get_divisors_ver()
386 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_get_divisors()  local
412 				divider->m = m >> 3;  in clk_wzrd_get_divisors()
413 				divider->m_frac = (m - (divider->m << 3)) * 125;  in clk_wzrd_get_divisors()
414 				divider->d = d;  in clk_wzrd_get_divisors()
415 				divider->o = o >> 3;  in clk_wzrd_get_divisors()
416 				divider->o_frac = (o - (divider->o << 3)) * 125;  in clk_wzrd_get_divisors()
423 static int clk_wzrd_reconfig(struct clk_wzrd_divider *divider, void __iomem *div_addr)  in clk_wzrd_reconfig()  argument
429 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_reconfig()
438 	return readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_reconfig()
447 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_ver_all_nolock()  local
455 	writel(0, divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4));  in clk_wzrd_dynamic_ver_all_nolock()
457 	m = divider->m;  in clk_wzrd_dynamic_ver_all_nolock()
460 	regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
468 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
471 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
474 	value2 = divider->d;  in clk_wzrd_dynamic_ver_all_nolock()
478 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
481 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));  in clk_wzrd_dynamic_ver_all_nolock()
483 	value = divider->o;  in clk_wzrd_dynamic_ver_all_nolock()
485 	regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
499 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
502 	writel(regval, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
504 	div_addr = divider->base + WZRD_DR_INIT_VERSAL_OFFSET;  in clk_wzrd_dynamic_ver_all_nolock()
506 	return clk_wzrd_reconfig(divider, div_addr);  in clk_wzrd_dynamic_ver_all_nolock()
512 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_all_nolock()  local
521 	reg = FIELD_PREP(WZRD_CLKOUT_DIVIDE_MASK, divider->o) |  in clk_wzrd_dynamic_all_nolock()
522 	      FIELD_PREP(WZRD_CLKOUT0_FRAC_MASK, divider->o_frac);  in clk_wzrd_dynamic_all_nolock()
524 	writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 2));  in clk_wzrd_dynamic_all_nolock()
525 	reg = FIELD_PREP(WZRD_CLKFBOUT_MULT_MASK, divider->m) |  in clk_wzrd_dynamic_all_nolock()
526 	      FIELD_PREP(WZRD_CLKFBOUT_MULT_FRAC_MASK, divider->m_frac) |  in clk_wzrd_dynamic_all_nolock()
527 	      FIELD_PREP(WZRD_DIVCLK_DIVIDE_MASK, divider->d);  in clk_wzrd_dynamic_all_nolock()
528 	writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 0));  in clk_wzrd_dynamic_all_nolock()
529 	writel(0, divider->base + WZRD_CLK_CFG_REG(0, 3));  in clk_wzrd_dynamic_all_nolock()
530 	div_addr = divider->base + WZRD_DR_INIT_REG_OFFSET;  in clk_wzrd_dynamic_all_nolock()
531 	return clk_wzrd_reconfig(divider, div_addr);  in clk_wzrd_dynamic_all_nolock()
537 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_all()  local
541 	spin_lock_irqsave(divider->lock, flags);  in clk_wzrd_dynamic_all()
545 	spin_unlock_irqrestore(divider->lock, flags);  in clk_wzrd_dynamic_all()
553 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_all_ver()  local
557 	spin_lock_irqsave(divider->lock, flags);  in clk_wzrd_dynamic_all_ver()
561 	spin_unlock_irqrestore(divider->lock, flags);  in clk_wzrd_dynamic_all_ver()
569 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_rate_all()  local
573 	reg = readl(divider->base + WZRD_CLK_CFG_REG(0, 0));  in clk_wzrd_recalc_rate_all()
577 	reg = readl(divider->base + WZRD_CLK_CFG_REG(0, 2));  in clk_wzrd_recalc_rate_all()
588 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_rate_all_ver()  local
592 	edge = !!(readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_1)) &  in clk_wzrd_recalc_rate_all_ver()
595 	reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_2));  in clk_wzrd_recalc_rate_all_ver()
603 	regl = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4)) &  in clk_wzrd_recalc_rate_all_ver()
606 		regl = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_3))  in clk_wzrd_recalc_rate_all_ver()
615 	reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_1));  in clk_wzrd_recalc_rate_all_ver()
620 	reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_2));  in clk_wzrd_recalc_rate_all_ver()
635 	edged = !!(readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_DESKEW_2)) &  in clk_wzrd_recalc_rate_all_ver()
637 	reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));  in clk_wzrd_recalc_rate_all_ver()
647 	return divider_recalc_rate(hw, parent_rate, div, divider->table,  in clk_wzrd_recalc_rate_all_ver()
648 			divider->flags, divider->width);  in clk_wzrd_recalc_rate_all_ver()
654 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_determine_rate_all()  local
662 	m = divider->m;  in clk_wzrd_determine_rate_all()
663 	d = divider->d;  in clk_wzrd_determine_rate_all()
664 	o = divider->o;  in clk_wzrd_determine_rate_all()
666 	req->rate = div_u64(req->best_parent_rate * (m * 1000 + divider->m_frac),  in clk_wzrd_determine_rate_all()
667 			    d * (o * 1000 + divider->o_frac));  in clk_wzrd_determine_rate_all()
674 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_ver_determine_rate_all()  local
683 	m = divider->m;  in clk_wzrd_ver_determine_rate_all()
684 	d = divider->d;  in clk_wzrd_ver_determine_rate_all()
685 	o = divider->o;  in clk_wzrd_ver_determine_rate_all()
689 					divider->table,  in clk_wzrd_ver_determine_rate_all()
690 					divider->flags, divider->width);  in clk_wzrd_ver_determine_rate_all()
729 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_ratef()  local
730 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_recalc_ratef()
733 	div = val & div_mask(divider->width);  in clk_wzrd_recalc_ratef()
745 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_reconfig_f()  local
746 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_dynamic_reconfig_f()
763 	err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_dynamic_reconfig_f()
771 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig_f()
773 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig_f()
776 	return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_dynamic_reconfig_f()
1105 		dev_err(dev, "unable to register divider clock\n");  in clk_wzrd_register_output_clocks()
1145 			dev_err(dev, "unable to register divider clock\n");  in clk_wzrd_register_output_clocks()