212 	const struct stm32_div_cfg *divider = &data->dividers[div_id];  in stm32_divider_get_rate()  local
216 	val =  readl(base + divider->offset) >> divider->shift;  in stm32_divider_get_rate()
217 	val &= clk_div_mask(divider->width);  in stm32_divider_get_rate()
218 	div = _get_div(divider->table, val, divider->flags, divider->width);  in stm32_divider_get_rate()
221 		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),  in stm32_divider_get_rate()
235 	const struct stm32_div_cfg *divider = &data->dividers[div_id];  in stm32_divider_set_rate()  local
239 	value = divider_get_val(rate, parent_rate, divider->table,  in stm32_divider_set_rate()
240 				divider->width, divider->flags);  in stm32_divider_set_rate()
244 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {  in stm32_divider_set_rate()
245 		val = clk_div_mask(divider->width) << (divider->shift + 16);  in stm32_divider_set_rate()
247 		val = readl(base + divider->offset);  in stm32_divider_set_rate()
248 		val &= ~(clk_div_mask(divider->width) << divider->shift);  in stm32_divider_set_rate()
251 	val |= (u32)value << divider->shift;  in stm32_divider_set_rate()
253 	writel(val, base + divider->offset);  in stm32_divider_set_rate()
358 	const struct stm32_div_cfg *divider;  in clk_stm32_divider_determine_rate()  local
363 	divider = &div->clock_data->dividers[div->div_id];  in clk_stm32_divider_determine_rate()
366 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in clk_stm32_divider_determine_rate()
369 		val =  readl(div->base + divider->offset) >> divider->shift;  in clk_stm32_divider_determine_rate()
370 		val &= clk_div_mask(divider->width);  in clk_stm32_divider_determine_rate()
374 						  divider->table,  in clk_stm32_divider_determine_rate()
375 						  divider->width,  in clk_stm32_divider_determine_rate()
376 						  divider->flags, val);  in clk_stm32_divider_determine_rate()
384 					      divider->table,  in clk_stm32_divider_determine_rate()
385 					      divider->width, divider->flags);  in clk_stm32_divider_determine_rate()
443 	const struct stm32_div_cfg *divider;  in clk_stm32_composite_determine_rate()  local
449 	divider = &composite->clock_data->dividers[composite->div_id];  in clk_stm32_composite_determine_rate()
452 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in clk_stm32_composite_determine_rate()
455 		val =  readl(composite->base + divider->offset) >> divider->shift;  in clk_stm32_composite_determine_rate()
456 		val &= clk_div_mask(divider->width);  in clk_stm32_composite_determine_rate()
459 					     divider->table, divider->width, divider->flags,  in clk_stm32_composite_determine_rate()
470 					 divider->table, divider->width, divider->flags);  in clk_stm32_composite_determine_rate()