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/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,dispcc-sc8280xp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SC8280XP
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
22 - qcom,sc8280xp-dispcc0
23 - qcom,sc8280xp-dispcc1
27 - description: AHB interface clock,
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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra124-dpaux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra DisplayPort AUX Interface
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra Display Port Auxiliary (DPAUX) pad controller manages two
16 controller.
18 When configured for DisplayPort AUX operation, the DPAUX controller
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/linux/Documentation/devicetree/bindings/display/xlnx/
H A Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
11 implements the display and audio pipelines based on the DisplayPort v1.2
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
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/linux/Documentation/devicetree/bindings/dma/xilinx/
H A Dxlnx,zynqmp-dpdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort DMA Controller
11 DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
16 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 - $ref: ../dma-controller.yaml#
22 "#dma-cells":
25 The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
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/linux/Documentation/gpu/
H A Dzynqmp.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 Xilinx ZynqMP Ultrascale+ DisplayPort Subsystem
7 This subsystem handles DisplayPort video and audio output on the ZynqMP. It
8 supports in-memory framebuffers with the DisplayPort DMA controller
9 (xilinx-dpdma), as well as "live" video and audio from the programmable logic
15 -------
18 though debugfs. The following files in /sys/kernel/debug/dri/X/DP-1/test/
19 control the DisplayPort test modes:
24 active/inactive will re-activate/re-deactivate test mode. When test
34 Enable/disable clock downspreading (spread-spectrum clocking) by
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H A Dtegra.rst6 the host1x controller. host1x supplies command streams, gathered from a push
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
22 outputs, such as RGB, HDMI, DSI, and DisplayPort.
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
40 device using a driver-provided function which will set up the bits specific to
48 -------------------------------
50 .. kernel-doc:: include/linux/host1x.h
52 .. kernel-doc:: drivers/gpu/host1x/bus.c
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/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_dpsub.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
47 * struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem
59 * @disp: The display controller
61 * @dp: The DisplayPort controller
/linux/Documentation/devicetree/bindings/display/
H A Ddp-aux-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dp-aux-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DisplayPort AUX bus
10 - Douglas Anderson <dianders@chromium.org>
13 DisplayPort controllers provide a control channel to the sinks that
20 of the DP controller under the "aux-bus" node.
29 const: aux-bus
32 $ref: panel/panel-common.yaml#
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/linux/sound/pci/hda/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "HD-Audio"
23 This option enables the HD-audio controller. Don't forget
27 will be called snd-hda-intel.
35 Say Y here to support the HDA controller present in NVIDIA
38 This options enables support for the HD Audio controller
43 will be called snd-hda-tegra.
50 Say Y here to include support for Azalia-compatible HDA controllers
54 will be called snd-hda-acpi.
59 bool "Build hwdep interface for HD-audio driver"
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/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,x1e80100-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abel Vesa <abel.vesa@linaro.org>
13 X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DP interfaces, etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,x1e80100-mdss
24 - description: Display AHB
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H A Dqcom,sc7180-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7180-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
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H A Dqcom,sm7150-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm7150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Danila Tikhonov <danila@jiaxyga.com>
13 SM7150 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm7150-mdss
24 - description: Display ahb clock from gcc
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H A Dqcom,sc7280-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7280-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
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H A Dqcom,sc8280xp-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sc8280xp-mdss
24 - description: Display AHB clock from gcc
25 - description: Display AHB clock from dispcc
[all …]
/linux/drivers/phy/qualcomm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
51 based PCIe controller.
69 with USB3 and DisplayPort controllers on Qualcomm chips.
110 Enable this legacy driver to support the QMP USB+DisplayPort Combo
124 controllers on Qualcomm chips. This driver supports the high-speed
133 Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm
164 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
167 Support for the USB high-speed ULPI compliant phy on Qualcomm
175 Enable support for the USB high-speed SNPS Femto phy on Qualcomm
[all …]
/linux/drivers/dma/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
65 Enable support for Altera / Intel mSGDMA controller.
94 Enable support for Audio DMA Controller found on Apple Silicon SoCs.
97 tristate "Arm DMA-350 support"
102 Enable support for the Arm DMA-350 controller.
110 Support the Atmel AHB DMA controller.
117 Support the Atmel XDMA controller.
120 tristate "Analog Devices AXI-DMAC DMA support"
126 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
127 controller is often used in Analog Devices' reference designs for FPGA
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dite,it6505.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Allen Chen <allen.chen@ite.com.tw>
13 - $ref: /schemas/sound/dai-common.yaml#
16 The IT6505 is a high-performance DisplayPort 1.1a transmitter,
17 fully compliant with DisplayPort 1.1a, HDCP 1.3 specifications.
19 and ensures robust transmission of high-quality uncompressed video
30 transmission of high-definition content. Users of the IT6505 need not
40 ovdd-supply:
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H A Dgoogle,cros-ec-anx7688.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/google,cros-ec-anx7688.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ChromeOS EC ANX7688 HDMI to DP Converter through Type-C Port
10 - Nicolas Boichat <drinkcat@chromium.org>
14 DisplayPort 1.3 Ultra-HDi (4096x2160p60). It is an Analogix ANX7688 chip
15 which is connected to and operated by the ChromeOS Embedded Controller
16 (See google,cros-ec.yaml). It is accessed using I2C tunneling through
18 (See google,cros-ec-i2c-tunnel.yaml).
[all …]
H A Danalogix,anx7814.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analogix ANX7814 SlimPort (Full-HD Transmitter)
10 - Andrzej Hajda <andrzej.hajda@intel.com>
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Robert Foss <robert.foss@linaro.org>
17 - analogix,anx7808
18 - analogix,anx7812
19 - analogix,anx7814
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/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-usbdp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3576-usbdp-phy
17 - rockchip,rk3588-usbdp-phy
22 "#phy-cells":
25 - PHY_TYPE_USB3
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H A Dsamsung,dp-video-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,dp-video-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC DisplayPort PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
17 - samsung,exynos5250-dp-video-phy
18 - samsung,exynos5420-dp-video-phy
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H A Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 hardware included with the Cadence MHDP DisplayPort controller. Torrent
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j7200-serdes-10g
24 - ti,j721e-serdes-10g
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/linux/drivers/platform/x86/
H A Dmeegopad_anx7428.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver to power on the Analogix ANX7428 USB Type-C crosspoint switch
4 * on MeeGoPad top-set boxes.
6 * The MeeGoPad T8 and T9 are Cherry Trail top-set boxes which
7 * use an ANX7428 to provide a Type-C port with USB3.1 Gen 1 and
8 * DisplayPort over Type-C alternate mode support.
12 * to send the right signal to the 4 highspeed pairs of the Type-C
16 * IOW the ANX7428 operates fully autonomous and to the x5-Z8350 SoC
17 * things look like there simply is a USB-3 Type-A connector and a
18 * separate DisplayPort connector. Except that the BIOS does not
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/linux/Documentation/devicetree/bindings/display/connector/
H A Ddp-connector.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/connector/dp-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DisplayPort Connector
10 - Tomi Valkeinen <tomi.valkeinen@ti.com>
14 const: dp-connector
20 - full-size
21 - mini
23 hpd-gpios:
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/linux/include/linux/platform_data/x86/
H A Dnvidia-wmi-ec-backlight.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #define WMI_BRIGHTNESS_GUID "603E9613-EF25-4338-A3D0-C46177516DB7"
12 * enum wmi_brightness_method - WMI method IDs
23 * enum wmi_brightness_mode - Operation mode for WMI-wrapped method
38 * enum wmi_brightness_source - Backlight brightness control source selection
41 * system's Embedded Controller (EC).
43 * DisplayPort AUX channel.
53 * struct wmi_brightness_args - arguments for the WMI-wrapped ACPI method

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