Lines Matching +full:displayport +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3576-usbdp-phy
17 - rockchip,rk3588-usbdp-phy
22 "#phy-cells":
25 - PHY_TYPE_USB3
26 - PHY_TYPE_DP
32 clock-names:
34 - const: refclk
35 - const: immortal
36 - const: pclk
37 - const: utmi
42 reset-names:
44 - const: init
45 - const: cmn
46 - const: lane
47 - const: pcs_apb
48 - const: pma_apb
50 phy-supply:
53 rockchip,dp-lane-mux:
54 $ref: /schemas/types.yaml#/definitions/uint32-array
60 An array of physical Type-C lanes indexes. Position of an entry
61 determines the DisplayPort (DP) lane index, while the value of an entry
62 indicates physical Type-C lane. The supported DP lanes number are 2 or 4.
63 e.g. for 2 lanes DP lanes map, we could have "rockchip,dp-lane-mux = <2,
64 3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
65 lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux =
66 <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
67 phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If
68 DP lanes are mapped by DisplayPort Alt mode, this property is not needed.
70 rockchip,u2phy-grf:
75 rockchip,usb-grf:
80 rockchip,usbdpphy-grf:
85 rockchip,vo-grf:
91 sbu1-dc-gpios:
93 GPIO connected to the SBU1 line of the USB-C connector via a big resistor
97 sbu2-dc-gpios:
99 GPIO connected to the SBU2 line of the USB-C connector via a big resistor
103 orientation-switch:
107 mode-switch:
114 A port node to link the PHY to a TypeC controller for the purpose of
118 - compatible
119 - reg
120 - clocks
121 - clock-names
122 - resets
123 - reset-names
124 - "#phy-cells"
129 - |
130 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
131 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
134 compatible = "rockchip,rk3588-usbdp-phy";
136 #phy-cells = <1>;
141 clock-names = "refclk", "immortal", "pclk", "utmi";
147 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
148 rockchip,u2phy-grf = <&usb2phy0_grf>;
149 rockchip,usb-grf = <&usb_grf>;
150 rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
151 rockchip,vo-grf = <&vo0_grf>;