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/linux/Documentation/devicetree/bindings/i2c/
H A Dsnps,designware-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare APB I2C Controller
10 - Jarkko Nikula <jarkko.nikula@linux.intel.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 const: mscc,ocelot-i2c
28 - description: Generic Synopsys DesignWare I2C controller
[all …]
/linux/arch/arm/boot/dts/st/
H A Dspear1310.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
[all …]
H A Dspear1340.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
16 compatible = "st,spear-spics-gpio";
18 st-spics,peripcfg-reg = <0x42c>;
19 st-spics,sw-enable-bit = <21>;
20 st-spics,cs-value-bit = <20>;
21 st-spics,cs-enable-mask = <3>;
22 st-spics,cs-enable-shift = <18>;
23 gpio-controller;
24 #gpio-cells = <2>;
29 compatible = "st,spear1340-miphy";
[all …]
H A Dspear13xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a9";
21 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
[all …]
/linux/arch/arm64/boot/dts/blaize/
H A Dblaize-blzp1600.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-a53";
[all …]
/linux/arch/arc/boot/dts/
H A Dabilis_tb10x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
12 compatible = "abilis,arc-tb10x";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
28 compatible = "snps,arc-timer";
30 interrupt-parent = <&intc>;
36 compatible = "snps,arc-timer";
41 #address-cells = <1>;
[all …]
H A Daxs10x_mb.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
18 interrupt-parent = <&mb_intc>;
20 creg_rst: reset-controller@11220 {
21 compatible = "snps,axs10x-reset";
22 #reset-cells = <1>;
27 compatible = "snps,axs10x-i2s-pll-clock";
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dsynopsys,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Synopsys DesignWare HDMI TX Controller
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 This document defines device tree properties for the Synopsys DesignWare HDMI
16 bindings for the platform-specific integrations of the DWC HDMI TX.
26 reg-io-width:
36 - description: The bus clock for either AHB and APB
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dk3dma.txt6 - compatible: Must be one of
7 - "hisilicon,k3-dma-1.0"
8 - "hisilicon,hisi-pcm-asp-dma-1.0"
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain one interrupt shared by all channel
11 - #dma-cells: see dma.txt, should be 1, para number
12 - dma-channels: physical channels supported
13 - dma-requests: virtual channels supported, each virtual channel
15 - clocks: clock required
21 compatible = "hisilicon,k3-dma-1.0";
[all …]
/linux/drivers/i2c/busses/
H A Di2c-designware-amdisp.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Based on Synopsys DesignWare I2C adapter driver.
13 #include "i2c-designware-core.h"
20 pm_runtime_disable(i2c_dev->dev); in amd_isp_dw_i2c_plat_pm_cleanup()
22 if (i2c_dev->shared_with_punit) in amd_isp_dw_i2c_plat_pm_cleanup()
23 pm_runtime_put_noidle(i2c_dev->dev); in amd_isp_dw_i2c_plat_pm_cleanup()
37 isp_i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*isp_i2c_dev), GFP_KERNEL); in amd_isp_dw_i2c_plat_probe()
39 return -ENOMEM; in amd_isp_dw_i2c_plat_probe()
40 isp_i2c_dev->dev = &pdev->dev; in amd_isp_dw_i2c_plat_probe()
42 pdev->dev.init_name = DRV_NAME; in amd_isp_dw_i2c_plat_probe()
[all …]
H A Di2c-designware-pcidrv.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver (master only).
5 * Based on the TI DAVINCI I2C adapter driver.
15 #include <linux/i2c.h>
27 #include "i2c-designware-core.h"
28 #include "i2c-ccgx-ucsi.h"
30 #define DRIVER_NAME "i2c-designware-pci"
91 /* NAVI-AMD HCNT/LCNT/SDA hold time */
107 switch (pdev->device) { in mfld_setup()
109 dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; in mfld_setup()
[all …]
H A Di2c-ccgx-ucsi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Instantiate UCSI device for Cypress CCGx Type-C controller.
4 * Derived from i2c-designware-pcidrv.c and i2c-nvidia-gpu.c.
7 #include <linux/i2c.h>
12 #include "i2c-ccgx-ucsi.h"
21 strscpy(info.type, "ccgx-ucsi", sizeof(info.type)); in i2c_new_ccgx_ucsi()
30 MODULE_DESCRIPTION("Instantiate UCSI device for Cypress CCGx Type-C controller");
H A Di2c-designware-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver.
5 * Based on the TI DAVINCI I2C adapter driver.
21 #include <linux/i2c.h>
35 #include "i2c-designware-core.h"
65 "incorrect slave-transmitter mode configuration",
72 *val = readl(dev->base + reg); in dw_reg_read()
81 writel(val, dev->base + reg); in dw_reg_write()
90 *val = swab32(readl(dev->base + reg)); in dw_reg_read_swab()
99 writel(swab32(val), dev->base + reg); in dw_reg_write_swab()
[all …]
H A Di2c-designware-baytrail.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel BayTrail PMIC I2C bus semaphore implementation
8 #include <linux/i2c.h>
13 #include "i2c-designware-core.h"
22 return -ENODEV; in i2c_dw_baytrail_probe_lock_support()
24 handle = ACPI_HANDLE(dev->dev); in i2c_dw_baytrail_probe_lock_support()
26 return -ENODEV; in i2c_dw_baytrail_probe_lock_support()
30 return -ENODEV; in i2c_dw_baytrail_probe_lock_support()
33 return -ENODEV; in i2c_dw_baytrail_probe_lock_support()
36 return -EPROBE_DEFER; in i2c_dw_baytrail_probe_lock_support()
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dcv180x.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include "cv18xx-reset.h"
13 #address-cells = <1>;
14 #size-cells = <1>;
17 compatible = "fixed-clock";
18 clock-output-names = "osc_25m";
19 #clock-cells = <0>;
[all …]
H A Dsg2044.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/clock/sophgo,sg2044-pll.h>
7 #include <dt-bindings/clock/sophgo,sg2044-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/pinctrl-sg2044.h>
12 #include "sg2044-cpus.dtsi"
13 #include "sg2044-reset.h"
24 compatible = "fixed-clock";
25 clock-output-names = "osc";
[all …]
/linux/arch/mips/boot/dts/mscc/
H A Djaguar2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
29 cpuintc: interrupt-controller {
30 #address-cells = <0>;
31 #interrupt-cells = <1>;
32 interrupt-controller;
33 compatible = "mti,cpu-interrupt-controller";
[all …]
/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
21 * Since this is a non-ratified draft specification, the kernel does not
[all …]
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/linux/arch/arm/boot/dts/synaptics/
H A Dberlin2cd.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Marvell Armada 1500-mini (BG2CD) SoC";
17 #address-cells = <1>;
18 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a9";
[all …]
H A Dberlin2q.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
6 #include <dt-bindings/clock/berlin2q.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
12 #address-cells = <1>;
13 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/hi3670-clock.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
27 cpu-map {
[all …]
/linux/include/linux/soc/amd/
H A Disp4_misc.h1 // SPDX-License-Identifier: GPL-2.0+
10 #define AMDISP_I2C_ADAP_NAME "AMDISP DesignWare I2C adapter"
/linux/sound/soc/amd/
H A Dacp-rt5645.c33 #include <sound/soc-dapm.h>
37 #include <linux/i2c.h>
66 dev_err(rtd->dev, "can't set codec pll: %d\n", ret); in cz_aif1_hw_params()
73 dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret); in cz_aif1_hw_params()
86 codec = snd_soc_rtd_to_codec(rtd, 0)->component; in cz_init()
87 card = rtd->card; in cz_init()
97 dev_err(card->dev, "HP jack creation failed %d\n", ret); in cz_init()
111 DAILINK_COMP_ARRAY(COMP_CPU("designware-i2s.1")));
113 DAILINK_COMP_ARRAY(COMP_CPU("designware-i2s.2")));
116 DAILINK_COMP_ARRAY(COMP_CODEC("i2c-10EC5650:00", "rt5645-aif1")));
[all …]

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