| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | sdhci-st.txt | 57 - sd-uhs-ddr50: To enable the DDR50 in the mmcss.
109 sd-uhs-ddr50;
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| H A D | sdhci-am654.yaml | 103 ti,otap-del-sel-ddr50:
104 description: Output tap delay for SD UHS DDR50 timing
161 ti,itap-del-sel-ddr50:
162 description: Input tap delay for MMC DDR50 timing
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| H A D | sdhci-omap.txt | 19 "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104",
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| H A D | cdns,sdhci.yaml | 69 cdns,phy-input-delay-sd-uhs-ddr50:
70 description: Value of the delay in the input path for SD UHS DDR50 timing
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| H A D | mmc-controller.yaml | 160 sd-uhs-ddr50:
163 SD UHS DDR50 speed is supported.
348 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
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| H A D | brcm,sdhci-brcmstb.yaml | 93 sd-uhs-ddr50;
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| H A D | samsung,exynos-dw-mshc.yaml | 166 sd-uhs-ddr50;
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| /linux/arch/arm/boot/dts/st/ |
| H A D | stih410-b2120.dts | 41 sd-uhs-ddr50;
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| H A D | stih418-b2199.dts | 94 sd-uhs-ddr50;
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| H A D | stm32mp157c-ed1.dts | 365 sd-uhs-ddr50;
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| /linux/arch/arm64/boot/dts/broadcom/ |
| H A D | bcm2712-rpi-5-b.dts | 62 sd-uhs-ddr50;
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| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | dra72x-mmc-iodelay.dtsi | 17 * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
90 mmc1_pins_ddr50_rev10: mmc1-ddr50-rev10-pins {
101 mmc1_pins_ddr50_rev20: mmc1-ddr50-rev20-pins {
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| H A D | dra72-evm.dts | 94 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| H A D | dra72-evm-revc.dts | 124 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| H A D | dra76x-mmc-iodelay.dtsi | 15 * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
63 mmc1_pins_ddr50: mmc1-ddr50-pins {
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| H A D | dra7-evm.dts | 389 …pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50"…
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| H A D | dra71-evm.dts | 203 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| /linux/drivers/mmc/host/ |
| H A D | dw_mmc-k3.c | 84 {0}, /* 7: DDR50 */
96 {0}, /* 7: DDR50 */
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| H A D | sdhci-pxav3.c | 138 * According to erratum 'FE-2946959' both SDR50 and DDR50 in armada_38x_quirks()
145 …dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider up… in armada_38x_quirks()
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| H A D | sdhci-of-sparx5.c | 154 SDHCI_QUIRK2_NO_1_8_V, /* No sdr104, ddr50, etc */
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| /linux/arch/arm64/boot/dts/amd/ |
| H A D | elba.dtsi | 181 cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>;
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mm-phg.dts | 243 sd-uhs-ddr50;
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| /linux/arch/arm64/boot/dts/amlogic/ |
| H A D | meson-gxl-s905x-libretech-cc-v2.dts | 254 sd-uhs-ddr50;
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| /linux/drivers/mmc/core/ |
| H A D | host.c | 252 mmc_of_parse_timing_phase(dev, "clk-phase-uhs-ddr50", in mmc_of_parse_clk_phase()
367 if (device_property_read_bool(dev, "sd-uhs-ddr50")) in mmc_of_parse()
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| /linux/arch/arm64/boot/dts/xilinx/ |
| H A D | zynqmp-sck-kv-g-revB.dtso | 157 clk-phase-uhs-ddr50 = <126>, <48>;
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