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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dqca,ath79-cpu-intc.txt3 On most SoC the IRQ controller need to flush the DDR FIFO before running
5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
9 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
28 interrupt-controller {
29 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
[all …]
/linux/drivers/irqchip/
H A Dirq-ath79-cpu.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
7 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
18 #include <asm/mach-ath79/ath79.h>
27 * This array map the interrupt lines to the DDR write buffer channels.
31 -1, -1, -1, -1, -1, -1, -1, -1,
48 irq = fls(pending) - 1; in plat_irq_dispatch()
49 if (irq < ARRAY_SIZE(irq_wb_chan) && irq_wb_chan[irq] != -1) in plat_irq_dispatch()
63 node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells"); in ar79_cpu_intc_of_init()
70 node, "qca,ddr-wb-channel-interrupts", i, &irq); in ar79_cpu_intc_of_init()
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dqca,ath79-ddr-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The DDR controller of the AR7xxx and AR9xxx families provides an interface to
14 flush the FIFO between various devices and the DDR. This is mainly used by
21 - items:
22 - const: qca,ar9132-ddr-controller
[all …]
/linux/arch/mips/boot/dts/qca/
H A Dar9132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
22 cpuintc: interrupt-controller {
23 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
25 interrupt-controller;
26 #interrupt-cells = <1>;
[all …]
H A Dar9331.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
22 cpuintc: interrupt-controller {
23 compatible = "qca,ar7100-cpu-intc";
25 interrupt-controller;
26 #interrupt-cells = <1>;
[all …]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A Duncore-interconnect.json31 "BriefDescription": "FAF - request insert from TC.",
47 "BriefDescription": "FAF allocation -- sent to ADQ",
84 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
94 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
104 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
114 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
124 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
134 … "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
144 … "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
154 "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
[all …]
H A Duncore-cache.json273 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
279 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory st…
284 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
290 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory s…
295 …"BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory writ…
300 …"PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes iss…
305 …"BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory writ…
310 …"PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory wri…
343 …s from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory stat…
485 …icDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory contro…
[all …]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A Duncore-interconnect.json31 "BriefDescription": "FAF - request insert from TC.",
47 "BriefDescription": "FAF allocation -- sent to ADQ",
84 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
94 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
104 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
114 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
124 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
134 … "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
144 … "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
154 "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
[all …]
H A Duncore-cache.json273 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
279 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory st…
284 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
290 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory s…
295 …"BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory writ…
300 …"PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes iss…
305 …"BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory writ…
310 …"PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory wri…
343 …s from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory stat…
485 …icDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory contro…
[all …]
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A Duncore-interconnect.json49 …"BriefDescription": "Direct to UPI Transactions - Ignored due to lack of credits : All : Counts th…
494 "BriefDescription": "All Writes - All Channels",
503 "BriefDescription": "Full Non-ISOCH - All Channels",
512 "BriefDescription": "Non-Inclusive - All Channels",
521 "BriefDescription": "Non-Inclusive Miss - All Channels",
530 "BriefDescription": "Partial Non-ISOCH - All Channels",
539 "BriefDescription": "DDR, acting as Cache - All Channels",
549 "BriefDescription": "DDR - All Channels",
559 "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0",
569 "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
[all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Duncore-interconnect.json111 "BriefDescription": "FAF allocation -- sent to ADQ",
148 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
158 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
168 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
178 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
188 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
198 … "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
208 … "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
218 "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
228 "BriefDescription": "Misc Events - Set 1 : Lost Forward",
[all …]
H A Duncore-cache.json1223 …ed in Counter 0. The filtering available is found in the control register - threshold, invert an…
1337 "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed",
1343 …"PublicDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed : Counts t…
1348 "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Needed",
1354 …"PublicDescription": "Multi-socket cacheline directory state lookups : Snoop Needed : Counts the n…
1359 …"BriefDescription": "Multi-socket cacheline directory state updates; memory write due to directory…
1364 …"PublicDescription": "Counts only multi-socket cacheline directory state updates memory writes iss…
1369 …"BriefDescription": "Multi-socket cacheline directory state updates; memory write due to directory…
1374 …"PublicDescription": "Counts only multi-socket cacheline directory state updates due to memory wri…
1401 "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
[all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A Duncore-interconnect.json47 …"BriefDescription": "Direct to UPI Transactions - Ignored due to lack of credits : All : Counts th…
492 "BriefDescription": "All Writes - All Channels",
501 "BriefDescription": "Full Non-ISOCH - All Channels",
510 "BriefDescription": "Non-Inclusive - All Channels",
519 "BriefDescription": "Non-Inclusive Miss - All Channels",
528 "BriefDescription": "Partial Non-ISOCH - All Channels",
537 "BriefDescription": "DDR, acting as Cache - All Channels",
547 "BriefDescription": "DDR - All Channels",
557 "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0",
567 "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
[all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-cache.json1113 …ed in Counter 0. The filtering available is found in the control register - threshold, invert an…
1249 "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
1255 …"PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles ei…
1260 "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
1266 …"PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of c…
1321 …s -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP directio…
1332 …s -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP directio…
1343 …s -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP directio…
1354 …s -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP directio…
1365 …T -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP directio…
[all …]