Lines Matching +full:ddr +full:- +full:wb +full:- +full:channels
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
7 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
18 #include <asm/mach-ath79/ath79.h>
27 * This array map the interrupt lines to the DDR write buffer channels.
31 -1, -1, -1, -1, -1, -1, -1, -1,
48 irq = fls(pending) - 1; in plat_irq_dispatch()
49 if (irq < ARRAY_SIZE(irq_wb_chan) && irq_wb_chan[irq] != -1) in plat_irq_dispatch()
63 node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells"); in ar79_cpu_intc_of_init()
70 node, "qca,ddr-wb-channel-interrupts", i, &irq); in ar79_cpu_intc_of_init()
75 node, "qca,ddr-wb-channels", in ar79_cpu_intc_of_init()
76 "#qca,ddr-wb-channel-cells", in ar79_cpu_intc_of_init()
86 IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",